diff options
| author |   Scott Wood <scottwood@freescale.com> | 2011-01-17 14:25:28 -0600 |
|---|---|---|
| committer |   Kumar Gala <galak@kernel.crashing.org> | 2011-03-15 13:48:16 -0500 |
| commit | 6820fead714d57012428c96266e86105e39075e0 (patch) | |
| tree | e24753dc62ab33a4d4c14236fe06d26cd69ba862 /Documentation/devicetree/bindings/powerpc | |
| parent | drivers/serial/ucc_uart.c: Add of_node_put to avoid memory leak (diff) | |
| download | linux-dev-6820fead714d57012428c96266e86105e39075e0.tar.xz linux-dev-6820fead714d57012428c96266e86105e39075e0.zip | |
powerpc/fsl_msi: Handle msi-available-ranges better
Now handles multiple ranges, doesn't make assumptions about interrupt
specifier format, and doesn't claim interrupts that don't correspond to an
available range.
Also has some better error checking.
The device tree binding is updated to clarify some existing assumptions.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'Documentation/devicetree/bindings/powerpc')
| -rw-r--r-- | Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt index bcc30bac6831..70558c3f3682 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt @@ -5,14 +5,21 @@ Required properties: first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572, etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on the parent type. + - reg : should contain the address and the length of the shared message interrupt register set. + - msi-available-ranges: use <start count> style section to define which msi interrupt can be used in the 256 msi interrupts. This property is optional, without this, all the 256 MSI interrupts can be used. + Each available range must begin and end on a multiple of 32 (i.e. + no splitting an individual MSI register or the associated PIC interrupt). + - interrupts : each one of the interrupts here is one entry per 32 MSIs, and routed to the host interrupt controller. the interrupts should - be set as edge sensitive. + be set as edge sensitive. If msi-available-ranges is present, only + the interrupts that correspond to available ranges shall be present. + - interrupt-parent: the phandle for the interrupt controller that services interrupts for this device. for 83xx cpu, the interrupts are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed |