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authorGregory CLEMENT <gregory.clement@bootlin.com>2018-02-28 15:27:23 +0100
committerHerbert Xu <herbert@gondor.apana.org.au>2018-03-09 22:45:45 +0800
commitb166be0044913a4ce03564e7c81f172025d78867 (patch)
treec9fb534a996380303457673a28e9babff26c4d4e /Documentation/devicetree/bindings/rng
parenthwrng: omap - Remove useless test before clk_disable_unprepare (diff)
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hwrng: omap - Fix clock resource by adding a register clock
On Armada 7K/8K we need to explicitly enable the register clock. This clock is optional because not all the SoCs using this IP need it but at least for Armada 7K/8K it is actually mandatory. The binding documentation is updating accordingly. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'Documentation/devicetree/bindings/rng')
-rw-r--r--Documentation/devicetree/bindings/rng/omap_rng.txt7
1 files changed, 6 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/rng/omap_rng.txt b/Documentation/devicetree/bindings/rng/omap_rng.txt
index 9cf7876ab434..ea434ce50f36 100644
--- a/Documentation/devicetree/bindings/rng/omap_rng.txt
+++ b/Documentation/devicetree/bindings/rng/omap_rng.txt
@@ -13,7 +13,12 @@ Required properties:
- interrupts : the interrupt number for the RNG module.
Used for "ti,omap4-rng" and "inside-secure,safexcel-eip76"
- clocks: the trng clock source. Only mandatory for the
- "inside-secure,safexcel-eip76" compatible.
+ "inside-secure,safexcel-eip76" compatible, the second clock is
+ needed for the Armada 7K/8K SoCs
+- clock-names: mandatory if there is a second clock, in this case the
+ name must be "core" for the first clock and "reg" for the second
+ one
+
Example:
/* AM335x */