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| author |   Michael Walle <michael@walle.cc> | 2020-03-07 10:13:01 +0100 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-03-12 10:02:00 +0100 |
| commit | c75b1fddae6c8e3fc89cd66bef056af782b05ea0 (patch) | |
| tree | 0310d222eefab0c73967001d53bc06778a88da1f /Documentation/devicetree/bindings/serial/fsl-lpuart.txt | |
| parent | tty: serial: fsl_lpuart: add LS1028A earlycon support (diff) | |
| download | linux-dev-c75b1fddae6c8e3fc89cd66bef056af782b05ea0.tar.xz linux-dev-c75b1fddae6c8e3fc89cd66bef056af782b05ea0.zip | |
dt-bindings: serial: lpuart: add ls1028a compatibility
Add the LS1028A SoC compatibility string to the lpuart devicetree
bindings documentation.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200307091302.14881-1-michael@walle.cc
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation/devicetree/bindings/serial/fsl-lpuart.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/serial/fsl-lpuart.txt | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt index c904e2e68332..e7448b92dd9d 100644 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt @@ -6,6 +6,8 @@ Required properties: on Vybrid vf610 SoC with 8-bit register organization - "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated on LS1021A SoC with 32-bit big-endian register organization + - "fsl,ls1028a-lpuart" for lpuart compatible with the one integrated + on LS1028A SoC with 32-bit little-endian register organization - "fsl,imx7ulp-lpuart" for lpuart compatible with the one integrated on i.MX7ULP SoC with 32-bit little-endian register organization - "fsl,imx8qxp-lpuart" for lpuart compatible with the one integrated @@ -15,10 +17,10 @@ Required properties: - reg : Address and length of the register set for the device - interrupts : Should contain uart interrupt - clocks : phandle + clock specifier pairs, one for each entry in clock-names -- clock-names : For vf610/ls1021a/imx7ulp, "ipg" clock is for uart bus/baud - clock. For imx8qxp lpuart, "ipg" clock is bus clock that is used to access - lpuart controller registers, it also requires "baud" clock for module to - receive/transmit data. +- clock-names : For vf610/ls1021a/ls1028a/imx7ulp, "ipg" clock is for uart + bus/baud clock. For imx8qxp lpuart, "ipg" clock is bus clock that is used + to access lpuart controller registers, it also requires "baud" clock for + module to receive/transmit data. Optional properties: - dmas: A list of two dma specifiers, one for each entry in dma-names. |