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authorDilip Kota <dkota@codeaurora.org>2018-10-03 19:14:23 +0530
committerMark Brown <broonie@kernel.org>2018-10-11 15:27:57 +0100
commita8a398b833f33a1efb8352fcd9f03a354fb387d9 (patch)
treea88deb07fa1ba33366032bd13f79ffc229f56a77 /Documentation/devicetree/bindings/soc
parentspi: rockchip: simplify spi enable logic (diff)
downloadlinux-dev-a8a398b833f33a1efb8352fcd9f03a354fb387d9.tar.xz
linux-dev-a8a398b833f33a1efb8352fcd9f03a354fb387d9.zip
dt-bindings: soc: qcom: Remove SPI controller maximum frequency binding
SPI controller driver should maintain the maximum frequency of the controller instead of relying on device tree bindings. Because maximum frequency is specific property of SPI controller. Signed-off-by: Dilip Kota <dkota@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Alok Chauhan <alokc@codeaurora.org> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/soc')
-rw-r--r--Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt2
1 files changed, 0 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
index ff92e5a41bed..b9d0c216df8c 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
@@ -60,7 +60,6 @@ Required properties:
- interrupts: Must contain SPI controller interrupts.
- clock-names: Must contain "se".
- clocks: Serial engine core clock needed by the device.
-- spi-max-frequency: Specifies maximum SPI clock frequency, units - Hz.
- #address-cells: Must be <1> to define a chip select address on
the SPI bus.
- #size-cells: Must be <0>.
@@ -112,7 +111,6 @@ Example:
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qup_1_spi_2_active>;
pinctrl-1 = <&qup_1_spi_2_sleep>;
- spi-max-frequency = <19200000>;
#address-cells = <1>;
#size-cells = <0>;
};