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author | Linus Torvalds <torvalds@linux-foundation.org> | 2019-07-09 09:17:59 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2019-07-09 09:17:59 -0700 |
commit | c6b6cebbc597aaf7d941f781b5fc114c58cc3352 (patch) | |
tree | a99ad03f0f53552338db140f34c325e47c6b54e4 /Documentation/devicetree/bindings/spi/spi-pl022.yaml | |
parent | Merge tag 'regulator-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator (diff) | |
parent | Merge remote-tracking branch 'spi/topic/pump-rt' into spi-next (diff) | |
download | linux-dev-c6b6cebbc597aaf7d941f781b5fc114c58cc3352.tar.xz linux-dev-c6b6cebbc597aaf7d941f781b5fc114c58cc3352.zip |
Merge tag 'spi-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown:
"For the most part this is a quiet release for SPI, though there's
several of the more widely used drivers that have had some fairly
substantial development done on them, mainly improving performance and
adding support for some more obscure use cases.
Summary:
- Support for configuring a minimum time for chip select to be
deasserted between transfers from Martin Sperl.
- A rework of the ACPI device instantiation code from Ard Biesheuvel.
- Fairly substantial development on the AT91 USART, BCM2835 and
Tegra114 drivers.
- New driver for Socionext SynQuacer"
* tag 'spi-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (58 commits)
spi: pxa2xx: Add support for Intel Elkhart Lake
spi: atmel-quadspi: fix resume call
spi: atmel-quadspi: void return type for atmel_qspi_init()
spi: pxa2xx: Set minimum transfer speed
spi: stm32-qspi: remove signal sensitive on completion
dt-bindings: spi: stm32-qspi: add dma properties
spi: uniphier: fix zero-length transfer
spi: uniphier: fix timeout error
spi/acpi: avoid spurious matches during slave enumeration
spi: spi-stm32-qspi: Remove CR_FTHRES_MASK usage
spi: fix ctrl->num_chipselect constraint
spi: spi-synquacer: Fixed build on architectures missing readsl/writesl series
spi/acpi: fix incorrect ACPI parent check
spi: don't open code list_for_each_entry_safe_reverse()
spi: No need to assign dummy value in spi_unregister_controller()
spi: Add a prototype for exported spi_set_cs_timing()
spi/acpi: enumerate all SPI slaves in the namespace
spi: qup: fix PIO/DMA transfers.
spi: Use struct_size() helper
spi: mediatek: add SPI_LSB_FIRST support
...
Diffstat (limited to 'Documentation/devicetree/bindings/spi/spi-pl022.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/spi/spi-pl022.yaml | 165 |
1 files changed, 165 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/spi/spi-pl022.yaml b/Documentation/devicetree/bindings/spi/spi-pl022.yaml new file mode 100644 index 000000000000..dfb697c69341 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-pl022.yaml @@ -0,0 +1,165 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/spi-pl022.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM PL022 SPI controller + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +allOf: + - $ref: "spi-controller.yaml#" + +# We need a select here so we don't match all nodes with 'arm,primecell' +select: + properties: + compatible: + contains: + const: arm,pl022 + required: + - compatible + +properties: + compatible: + items: + - const: arm,pl022 + - const: arm,primecell + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - enum: + - SSPCLK + - sspclk + - const: apb_pclk + + pl022,autosuspend-delay: + description: delay in ms following transfer completion before the + runtime power management system suspends the device. A setting of 0 + indicates no delay and the device will be suspended immediately. + $ref: "/schemas/types.yaml#/definitions/uint32" + + pl022,rt: + description: indicates the controller should run the message pump with realtime + priority to minimise the transfer latency on the bus (boolean) + type: boolean + + dmas: + description: + Two or more DMA channel specifiers following the convention outlined + in bindings/dma/dma.txt + minItems: 2 + maxItems: 32 + + dma-names: + description: + There must be at least one channel named "tx" for transmit and named "rx" + for receive. + minItems: 2 + maxItems: 32 + additionalItems: true + items: + - const: rx + - const: tx + +patternProperties: + "^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-f]+$": + type: object + # SPI slave nodes must be children of the SPI master node and can + # contain the following properties. + properties: + pl022,interface: + description: SPI interface type + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - enum: + - 0 # SPI + - 1 # Texas Instruments Synchronous Serial Frame Format + - 2 # Microwire (Half Duplex) + + pl022,com-mode: + description: Specifies the transfer mode + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - enum: + - 0 # interrupt mode + - 1 # polling mode + - 2 # DMA mode + default: 1 + + pl022,rx-level-trig: + description: Rx FIFO watermark level + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + maximum: 4 + + pl022,tx-level-trig: + description: Tx FIFO watermark level + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + maximum: 4 + + pl022,ctrl-len: + description: Microwire interface - Control length + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0x03 + maximum: 0x1f + + pl022,wait-state: + description: Microwire interface - Wait state + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - enum: [ 0, 1 ] + + pl022,duplex: + description: Microwire interface - Full/Half duplex + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - enum: [ 0, 1 ] + +required: + - compatible + - reg + - interrupts + +examples: + - | + spi@e0100000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xe0100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 31 0x4>; + dmas = <&dma_controller 23 1>, + <&dma_controller 24 0>; + dma-names = "rx", "tx"; + + m25p80@1 { + compatible = "st,m25p80"; + reg = <1>; + spi-max-frequency = <12000000>; + spi-cpol; + spi-cpha; + pl022,interface = <0>; + pl022,com-mode = <0x2>; + pl022,rx-level-trig = <0>; + pl022,tx-level-trig = <0>; + pl022,ctrl-len = <0x11>; + pl022,wait-state = <0>; + pl022,duplex = <0>; + }; + }; +... |