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author | Linus Torvalds <torvalds@linux-foundation.org> | 2019-09-19 13:48:37 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2019-09-19 13:48:37 -0700 |
commit | e3a008ac1213d99f5f1210adc9d2a1f60da10c3b (patch) | |
tree | 4d4d13f81cb06eb278de0bf601346b73f38534be /Documentation/devicetree/bindings/spi | |
parent | Merge tag 'dma-mapping-5.4' of git://git.infradead.org/users/hch/dma-mapping (diff) | |
parent | of: restore old handling of cells_name=NULL in of_*_phandle_with_args() (diff) | |
download | linux-dev-e3a008ac1213d99f5f1210adc9d2a1f60da10c3b.tar.xz linux-dev-e3a008ac1213d99f5f1210adc9d2a1f60da10c3b.zip |
Merge tag 'devicetree-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull Devicetree updates from Rob Herring:
- a bunch of DT binding conversions to DT schema format
- clean-ups of the Arm idle-states binding
- support a default number of cells in of_for_each_phandle() when the
cells name is missing
- expose dtbs_check and dt_binding_check in the make help
- convert writting-schema.md to ReST
- HiSilicon reset controller binding updates
- add documentation for MT8516 RNG
* tag 'devicetree-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (46 commits)
of: restore old handling of cells_name=NULL in of_*_phandle_with_args()
bus: qcom: fix spelling mistake "ambigous" -> "ambiguous"
of: Let of_for_each_phandle fallback to non-negative cell_count
iommu: pass cell_count = -1 to of_for_each_phandle with cells_name
dt-bindings: arm: Convert Realtek board/soc bindings to json-schema
dt-bindings: arm: Convert Actions Semi bindings to jsonschema
dt-bindings: Correct spelling in example schema
dt-bindings: cpu: Add a support cpu type for cortex-a55
dt-bindings: gpu: mali-midgard: Add samsung exynos5250 compatible
dt-bindings: arm: idle-states: Move exit-latency-us explanation
dt-bindings: arm: idle-states: Add punctuation to improve readability
dt-bindings: arm: idle-states: Correct "constraint guarantees"
dt-bindings: arm: idle-states: Correct references to wake-up delay
dt-bindings: arm: idle-states: Use "e.g." and "i.e." consistently
pinctrl-mcp23s08: Fix property-name in dt-example
dt-bindings: Clarify interrupts-extended usage
dt-bindings: Convert Arm Mali Utgard GPU to DT schema
dt-bindings: Convert Arm Mali Bifrost GPU to DT schema
dt-bindings: Convert Arm Mali Midgard GPU to DT schema
dt-bindings: irq: Convert Allwinner NMI Controller to a schema
...
Diffstat (limited to 'Documentation/devicetree/bindings/spi')
3 files changed, 120 insertions, 55 deletions
diff --git a/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml new file mode 100644 index 000000000000..49b617c98ae7 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 BayLibre, SAS +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/spi/amlogic,meson-gx-spicc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic Meson SPI Communication Controller + +maintainers: + - Neil Armstrong <narmstrong@baylibre.com> + +allOf: + - $ref: "spi-controller.yaml#" + +description: | + The Meson SPICC is a generic SPI controller for general purpose Full-Duplex + communications with dedicated 16 words RX/TX PIO FIFOs. + +properties: + compatible: + enum: + - amlogic,meson-gx-spicc # SPICC controller on Amlogic GX and compatible SoCs + - amlogic,meson-axg-spicc # SPICC controller on Amlogic AXG and compatible SoCs + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + resets: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + description: input clock for the baud rate generator + items: + - const: core + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +examples: + - | + spi@c1108d80 { + compatible = "amlogic,meson-gx-spicc"; + reg = <0xc1108d80 0x80>; + interrupts = <112>; + clocks = <&clk81>; + clock-names = "core"; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-switch@0 { + compatible = "micrel,ks8995m"; + spi-max-frequency = <1000000>; + reg = <0>; + }; + }; + diff --git a/Documentation/devicetree/bindings/spi/amlogic,meson6-spifc.yaml b/Documentation/devicetree/bindings/spi/amlogic,meson6-spifc.yaml new file mode 100644 index 000000000000..5f33c39d820b --- /dev/null +++ b/Documentation/devicetree/bindings/spi/amlogic,meson6-spifc.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 BayLibre, SAS +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/spi/amlogic,meson6-spifc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic Meson SPI Flash Controller + +maintainers: + - Neil Armstrong <narmstrong@baylibre.com> + +allOf: + - $ref: "spi-controller.yaml#" + +description: | + The Meson SPIFC is a controller optimized for communication with SPI + NOR memories, without DMA support and a 64-byte unified transmit / + receive buffer. + +properties: + compatible: + enum: + - amlogic,meson6-spifc # SPI Flash Controller on Meson6 and compatible SoCs + - amlogic,meson-gxbb-spifc # SPI Flash Controller on GXBB and compatible SoCs + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +examples: + - | + spi@c1108c80 { + compatible = "amlogic,meson6-spifc"; + reg = <0xc1108c80 0x80>; + clocks = <&clk81>; + #address-cells = <1>; + #size-cells = <0>; + + flash: flash@0 { + compatible = "spansion,m25p80", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; + }; + diff --git a/Documentation/devicetree/bindings/spi/spi-meson.txt b/Documentation/devicetree/bindings/spi/spi-meson.txt deleted file mode 100644 index b7f5e86fed22..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-meson.txt +++ /dev/null @@ -1,55 +0,0 @@ -Amlogic Meson SPI controllers - -* SPIFC (SPI Flash Controller) - -The Meson SPIFC is a controller optimized for communication with SPI -NOR memories, without DMA support and a 64-byte unified transmit / -receive buffer. - -Required properties: - - compatible: should be "amlogic,meson6-spifc" or "amlogic,meson-gxbb-spifc" - - reg: physical base address and length of the controller registers - - clocks: phandle of the input clock for the baud rate generator - - #address-cells: should be 1 - - #size-cells: should be 0 - - spi@c1108c80 { - compatible = "amlogic,meson6-spifc"; - reg = <0xc1108c80 0x80>; - clocks = <&clk81>; - #address-cells = <1>; - #size-cells = <0>; - }; - -* SPICC (SPI Communication Controller) - -The Meson SPICC is generic SPI controller for general purpose Full-Duplex -communications with dedicated 16 words RX/TX PIO FIFOs. - -Required properties: - - compatible: should be: - "amlogic,meson-gx-spicc" on Amlogic GX and compatible SoCs. - "amlogic,meson-axg-spicc" on Amlogic AXG and compatible SoCs - - reg: physical base address and length of the controller registers - - interrupts: The interrupt specifier - - clock-names: Must contain "core" - - clocks: phandle of the input clock for the baud rate generator - - #address-cells: should be 1 - - #size-cells: should be 0 - -Optional properties: - - resets: phandle of the internal reset line - -See ../spi/spi-bus.txt for more details on SPI bus master and slave devices -required and optional properties. - -Example : - spi@c1108d80 { - compatible = "amlogic,meson-gx-spicc"; - reg = <0xc1108d80 0x80>; - interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "core"; - clocks = <&clk81>; - #address-cells = <1>; - #size-cells = <0>; - }; |