diff options
| author |   Chris Brandt <chris.brandt@renesas.com> | 2017-01-27 15:02:14 -0500 |
|---|---|---|
| committer |   Daniel Lezcano <daniel.lezcano@linaro.org> | 2017-02-07 20:58:30 +0100 |
| commit | a1966cd29d5fee2fada47b82dcb73126eb65dfd4 (patch) | |
| tree | 4a5f01103b7fcdefa3fef80f2960c26e8120e120 /Documentation/devicetree/bindings/timer | |
| parent | clocksource/drivers/tcb_clksrc: Use 32 bit tcb as sched_clock (diff) | |
| download | linux-dev-a1966cd29d5fee2fada47b82dcb73126eb65dfd4.tar.xz linux-dev-a1966cd29d5fee2fada47b82dcb73126eb65dfd4.zip | |
clocksource/drivers/ostm: Document renesas-ostm timer DT bindings
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/timer')
| -rw-r--r-- | Documentation/devicetree/bindings/timer/renesas,ostm.txt | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/timer/renesas,ostm.txt b/Documentation/devicetree/bindings/timer/renesas,ostm.txt new file mode 100644 index 000000000000..be3ae0fdf775 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/renesas,ostm.txt @@ -0,0 +1,30 @@ +* Renesas OS Timer (OSTM) + +The OSTM is a multi-channel 32-bit timer/counter with fixed clock +source that can operate in either interval count down timer or free-running +compare match mode. + +Channels are independent from each other. + +Required Properties: + + - compatible: must be one or more of the following: + - "renesas,r7s72100-ostm" for the r7s72100 OSTM + - "renesas,ostm" for any OSTM + This is a fallback for the above renesas,*-ostm entries + + - reg: base address and length of the register block for a timer channel. + + - interrupts: interrupt specifier for the timer channel. + + - clocks: clock specifier for the timer channel. + +Example: R7S72100 (RZ/A1H) OSTM node + + ostm0: timer@fcfec000 { + compatible = "renesas,r7s72100-ostm", "renesas,ostm"; + reg = <0xfcfec000 0x30>; + interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>; + clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; + power-domains = <&cpg_clocks>; + }; |