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| author |   Amit Nischal <anischal@codeaurora.org> | 2018-05-09 17:02:30 +0530 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2018-06-01 11:49:07 -0700 |
| commit | 84b66b2116031fc4e5b73ce304c6a6a2e08778a3 (patch) | |
| tree | 66264a56507a37d9ef9126f01bc1e525ed660902 /Documentation/devicetree | |
| parent | clk: qcom: Add Global Clock controller (GCC) driver for SDM845 (diff) | |
| download | linux-dev-84b66b2116031fc4e5b73ce304c6a6a2e08778a3.tar.xz linux-dev-84b66b2116031fc4e5b73ce304c6a6a2e08778a3.zip | |
dt-bindings: clock: Introduce QCOM Video clock bindings
Add device tree bindings for video clock controller for
Qualcomm Technology Inc's SoCs.
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/qcom,videocc.txt | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.txt b/Documentation/devicetree/bindings/clock/qcom,videocc.txt new file mode 100644 index 000000000000..e7c035afa778 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.txt @@ -0,0 +1,19 @@ +Qualcomm Video Clock & Reset Controller Binding +----------------------------------------------- + +Required properties : +- compatible : shall contain "qcom,sdm845-videocc" +- reg : shall contain base register location and length +- #clock-cells : from common clock binding, shall contain 1. +- #power-domain-cells : from generic power domain binding, shall contain 1. + +Optional properties : +- #reset-cells : from common reset binding, shall contain 1. + +Example: + videocc: clock-controller@ab00000 { + compatible = "qcom,sdm845-videocc"; + reg = <0xab00000 0x10000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; |