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| author |   Gabor Juhos <juhosg@openwrt.org> | 2012-09-08 14:02:21 +0200 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2012-10-01 11:37:15 +0200 |
| commit | 97541ccfb9db2bb9cd1dde6344d5834438d14bda (patch) | |
| tree | fbdcb943e76ee180c6025a2f7f5645c101014f00 /Documentation/devicetree | |
| parent | MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x (diff) | |
| download | linux-dev-97541ccfb9db2bb9cd1dde6344d5834438d14bda.tar.xz linux-dev-97541ccfb9db2bb9cd1dde6344d5834438d14bda.zip | |
MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLs
Besides the CPU and DDR PLLs, the CPU and DDR frequencies
can be derived from other PLLs in the SRIF block on the
AR934x SoCs. The current code does not checks if the SRIF
PLLs are used and this can lead to incorrectly calculated
CPU/DDR frequencies.
Fix it by calculating the frequencies from SRIF PLLs if
those are used on a given board.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: <stable@vger.kernel.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4324/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'Documentation/devicetree')
0 files changed, 0 insertions, 0 deletions