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authorLinus Torvalds <torvalds@linux-foundation.org>2021-02-24 09:38:36 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2021-02-24 09:38:36 -0800
commit825d1508750c0cad13e5da564d47a6d59c7612d6 (patch)
tree0f173e39ed7638ffcc52b965f933aa7762500111 /Documentation/driver-api
parentMerge tag 'libnvdimm-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm (diff)
parentcxl/mem: Fix potential memory leak (diff)
downloadlinux-dev-825d1508750c0cad13e5da564d47a6d59c7612d6.tar.xz
linux-dev-825d1508750c0cad13e5da564d47a6d59c7612d6.zip
Merge tag 'cxl-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm
Pull initial support for CXL (Compute Express Link) from Dan Williams: "Introduce an initial driver for CXL 2.0 Type-3 Memory Devices. CXL is Compute Express Link which released the 2.0 specification in November. The Linux relevant changes in CXL 2.0 are support for an OS to dynamically assign address space to memory devices, support for switches, persistent memory, and hotplug. A Type-3 Memory Device is a PCI enumerated device presenting the CXL Memory Device Class Code and implementing the CXL.mem protocol. CXL.mem allows device to advertise CPU and I/O coherent memory to the system, i.e. typical "System RAM" and "Persistent Memory" in Linux /proc/iomem terms. In addition to the CXL.mem fast path there is an administrative command hardware mailbox interface for maintenance and provisioning. It is this command interface that is the focus of the initial driver. With this driver a CXL device that is mapped by the BIOS can be administered by Linux. Linux support for CXL PMEM and dynamic CXL address space management are to be implemented post v5.12" Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> 4cdadfd5e0a7 ("cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpoints") 13237183c735 ("cxl/mem: Add a "RAW" send command") 472b1ce6e9d6 ("cxl/mem: Enable commands via CEL") 57ee605b976c ("cxl/mem: Add set of informational commands") Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> 8adaf747c9f0 ("cxl/mem: Find device capabilities") b39cb1052a5c ("cxl/mem: Register CXL memX devices") * tag 'cxl-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm: cxl/mem: Fix potential memory leak cxl/mem: Return -EFAULT if copy_to_user() fails MAINTAINERS: Add maintainers of the CXL driver cxl/mem: Add set of informational commands cxl/mem: Enable commands via CEL cxl/mem: Add a "RAW" send command cxl/mem: Add basic IOCTL interface cxl/mem: Register CXL memX devices cxl/mem: Find device capabilities cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpoints
Diffstat (limited to 'Documentation/driver-api')
-rw-r--r--Documentation/driver-api/cxl/index.rst12
-rw-r--r--Documentation/driver-api/cxl/memory-devices.rst46
-rw-r--r--Documentation/driver-api/index.rst1
3 files changed, 59 insertions, 0 deletions
diff --git a/Documentation/driver-api/cxl/index.rst b/Documentation/driver-api/cxl/index.rst
new file mode 100644
index 000000000000..036e49553542
--- /dev/null
+++ b/Documentation/driver-api/cxl/index.rst
@@ -0,0 +1,12 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+====================
+Compute Express Link
+====================
+
+.. toctree::
+ :maxdepth: 1
+
+ memory-devices
+
+.. only:: subproject and html
diff --git a/Documentation/driver-api/cxl/memory-devices.rst b/Documentation/driver-api/cxl/memory-devices.rst
new file mode 100644
index 000000000000..1bad466f9167
--- /dev/null
+++ b/Documentation/driver-api/cxl/memory-devices.rst
@@ -0,0 +1,46 @@
+.. SPDX-License-Identifier: GPL-2.0
+.. include:: <isonum.txt>
+
+===================================
+Compute Express Link Memory Devices
+===================================
+
+A Compute Express Link Memory Device is a CXL component that implements the
+CXL.mem protocol. It contains some amount of volatile memory, persistent memory,
+or both. It is enumerated as a PCI device for configuration and passing
+messages over an MMIO mailbox. Its contribution to the System Physical
+Address space is handled via HDM (Host Managed Device Memory) decoders
+that optionally define a device's contribution to an interleaved address
+range across multiple devices underneath a host-bridge or interleaved
+across host-bridges.
+
+Driver Infrastructure
+=====================
+
+This section covers the driver infrastructure for a CXL memory device.
+
+CXL Memory Device
+-----------------
+
+.. kernel-doc:: drivers/cxl/mem.c
+ :doc: cxl mem
+
+.. kernel-doc:: drivers/cxl/mem.c
+ :internal:
+
+CXL Bus
+-------
+.. kernel-doc:: drivers/cxl/bus.c
+ :doc: cxl bus
+
+External Interfaces
+===================
+
+CXL IOCTL Interface
+-------------------
+
+.. kernel-doc:: include/uapi/linux/cxl_mem.h
+ :doc: UAPI
+
+.. kernel-doc:: include/uapi/linux/cxl_mem.h
+ :internal:
diff --git a/Documentation/driver-api/index.rst b/Documentation/driver-api/index.rst
index 9d9af54d68c5..9ba74e86751b 100644
--- a/Documentation/driver-api/index.rst
+++ b/Documentation/driver-api/index.rst
@@ -35,6 +35,7 @@ available subsections can be seen below.
usb/index
firewire
pci/index
+ cxl/index
spi
i2c
ipmb