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| author |   Dan Williams <dan.j.williams@intel.com> | 2021-02-16 20:09:52 -0800 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2021-02-16 20:36:38 -0800 |
| commit | b39cb1052a5cf41bc12201ec1c0ddae5cb8be868 (patch) | |
| tree | 13079eddea29561e8e20cd7f388e143ec97494ca /Documentation/driver-api | |
| parent | cxl/mem: Find device capabilities (diff) | |
| download | linux-dev-b39cb1052a5cf41bc12201ec1c0ddae5cb8be868.tar.xz linux-dev-b39cb1052a5cf41bc12201ec1c0ddae5cb8be868.zip | |
cxl/mem: Register CXL memX devices
Create the /sys/bus/cxl hierarchy to enumerate:
* Memory Devices (per-endpoint control devices)
* Memory Address Space Devices (platform address ranges with
interleaving, performance, and persistence attributes)
* Memory Regions (active provisioned memory from an address space device
that is in use as System RAM or delegated to libnvdimm as Persistent
Memory regions).
For now, only the per-endpoint control devices are registered on the
'cxl' bus. However, going forward it will provide a mechanism to
coordinate cross-device interleave.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> (v2)
Link: https://lore.kernel.org/r/20210217040958.1354670-4-ben.widawsky@intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'Documentation/driver-api')
| -rw-r--r-- | Documentation/driver-api/cxl/memory-devices.rst | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/driver-api/cxl/memory-devices.rst b/Documentation/driver-api/cxl/memory-devices.rst index 43177e700d62..1fef2c0a167d 100644 --- a/Documentation/driver-api/cxl/memory-devices.rst +++ b/Documentation/driver-api/cxl/memory-devices.rst @@ -27,3 +27,8 @@ CXL Memory Device .. kernel-doc:: drivers/cxl/mem.c :internal: + +CXL Bus +------- +.. kernel-doc:: drivers/cxl/bus.c + :doc: cxl bus |