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authorLinus Torvalds <torvalds@linux-foundation.org>2022-08-05 14:13:45 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2022-08-05 14:13:45 -0700
commit74cae210a335d159f2eb822e261adee905b6951a (patch)
treed9dd967fe200c53e04d18c825860c2b2b7188fa5 /Documentation/networking/device_drivers/cellular/ssh:/git@git.zx2c4.com
parentMerge tag 'for-linus-5.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/uml (diff)
parentmtd: core: check partition before dereference (diff)
Merge tag 'mtd/for-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
Pull MTD updates from Richard Weinberger: "MTD core changes: - Dynamic partition support - Fix deadlock in sm_ftl - Various refcount fixes in maps, partitions and parser code - Integer overflow fixes in mtdchar - Support for Sercomm partitions NAND driver changes: - Clockrate fix for arasan - Add ATO25D1GA support - Double free fix for meson driver - Fix probe/remove methods in cafe NAND - Support unprotected spare data pages in qcom_nandc SPI NOR core changes: - move SECT_4K_PMC flag out of the core as it's a vendor specific flag - s/addr_width/addr_nbytes/g: address width means the number of IO lines used for the address, whereas in the code it is used as the number of address bytes. - do not change nor->addr_nbytes at SFDP parsing time. At the SFDP parsing time we should not change members of struct spi_nor, but instead fill members of struct spi_nor_flash_parameters which could later on be used by the callers. - track flash's internal address mode so that we can use 4B opcodes together with opcodes that don't have a 4B opcode correspondent. SPI NOR manufacturer drivers changes: - esmt: Rename "f25l32qa" flash name to "f25l32qa-2s". - micron-st: Skip FSR reading if SPI controller does not support it to allow flashes that support FSR to work even when attached to such SPI controllers. - spansion: Add s25hl-t/s25hs-t IDs and fixups" * tag 'mtd/for-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (53 commits) mtd: core: check partition before dereference mtd: spi-nor: fix spi_nor_spimem_setup_op() call in spi_nor_erase_{sector,chip}() mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups mtd: spi-nor: spansion: Add local function to discover page size mtd: spi-nor: core: Track flash's internal address mode mtd: spi-nor: core: Return error code from set_4byte_addr_mode() mtd: spi-nor: Do not change nor->addr_nbytes at SFDP parsing time mtd: spi-nor: core: Shrink the storage size of the flash_info's addr_nbytes mtd: spi-nor: s/addr_width/addr_nbytes mtd: spi-nor: esmt: Use correct name of f25l32qa mtd: spi-nor: micron-st: Skip FSR reading if SPI controller does not support it MAINTAINERS: Use my kernel.org email mtd: rawnand: arasan: Fix clock rate in NV-DDR mtd: rawnand: arasan: Update NAND bus clock instead of system clock mtd: core: introduce of support for dynamic partitions dt-bindings: mtd: partitions: add additional example for qcom,smem-part dt-bindings: mtd: partitions: support label/name only partition mtd: spi-nor: move SECT_4K_PMC special handling mtd: dataflash: Add SPI ID table mtd: hyperbus: rpc-if: Fix RPM imbalance in probe error path ...
Diffstat (limited to 'Documentation/networking/device_drivers/cellular/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions
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/*
 * Copyright © 2016 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#ifndef __I915_FENCE_REG_H__
#define __I915_FENCE_REG_H__

#include <linux/list.h>
#include <linux/types.h>

struct drm_i915_gem_object;
struct drm_i915_private;
struct i915_ggtt;
struct i915_vma;
struct intel_gt;
struct sg_table;

#define I965_FENCE_PAGE 4096UL

struct i915_fence_reg {
	struct list_head link;
	struct drm_i915_private *i915;
	struct i915_vma *vma;
	atomic_t pin_count;
	int id;
	/**
	 * Whether the tiling parameters for the currently
	 * associated fence register have changed. Note that
	 * for the purposes of tracking tiling changes we also
	 * treat the unfenced register, the register slot that
	 * the object occupies whilst it executes a fenced
	 * command (such as BLT on gen2/3), as a "fence".
	 */
	bool dirty;
};

/* i915_gem_fence_reg.c */
struct i915_fence_reg *i915_reserve_fence(struct drm_i915_private *i915);
void i915_unreserve_fence(struct i915_fence_reg *fence);

void i915_gem_restore_fences(struct drm_i915_private *i915);

void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
				       struct sg_table *pages);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
					 struct sg_table *pages);

void i915_ggtt_init_fences(struct i915_ggtt *ggtt);

void intel_gt_init_swizzling(struct intel_gt *gt);

#endif