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| author |   Reinette Chatre <reinette.chatre@intel.com> | 2018-06-22 15:42:30 -0700 |
|---|---|---|
| committer |   Thomas Gleixner <tglx@linutronix.de> | 2018-06-24 15:35:48 +0200 |
| commit | 6fc0de37f663278af160e8e1f0c38b27e6c06206 (patch) | |
| tree | 2001f39bf5a067d0c43d2576f24ba6a2191999d7 /Documentation/x86 | |
| parent | x86/intel_rdt: Support L3 cache performance event of Broadwell (diff) | |
| download | linux-dev-6fc0de37f663278af160e8e1f0c38b27e6c06206.tar.xz linux-dev-6fc0de37f663278af160e8e1f0c38b27e6c06206.zip | |
x86/intel_rdt: Limit C-states dynamically when pseudo-locking active
Deeper C-states impact cache content through shrinking of the cache or
flushing entire cache to memory before reducing power to the cache.
Deeper C-states will thus negatively impact the pseudo-locked regions.
To avoid impacting pseudo-locked regions C-states are limited on
pseudo-locked region creation so that cores associated with the
pseudo-locked region are prevented from entering deeper C-states.
This is accomplished by requesting a CPU latency target which will
prevent the core from entering C6 across all supported platforms.
Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: fenghua.yu@intel.com
Cc: tony.luck@intel.com
Cc: vikas.shivappa@linux.intel.com
Cc: gavin.hindman@intel.com
Cc: jithu.joseph@intel.com
Cc: dave.hansen@intel.com
Cc: hpa@zytor.com
Link: https://lkml.kernel.org/r/1ef4f99dd6ba12fa6fb44c5a1141e75f952b9cd9.1529706536.git.reinette.chatre@intel.com
Diffstat (limited to 'Documentation/x86')
| -rw-r--r-- | Documentation/x86/intel_rdt_ui.txt | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/x86/intel_rdt_ui.txt b/Documentation/x86/intel_rdt_ui.txt index bcd0a6d2fcf8..acac30b67c62 100644 --- a/Documentation/x86/intel_rdt_ui.txt +++ b/Documentation/x86/intel_rdt_ui.txt @@ -461,8 +461,8 @@ in the cache via carefully configuring the CAT feature and controlling application behavior. There is no guarantee that data is placed in cache. Instructions like INVD, WBINVD, CLFLUSH, etc. can still evict “locked” data from cache. Power management C-states may shrink or -power off cache. It is thus recommended to limit the processor maximum -C-state, for example, by setting the processor.max_cstate kernel parameter. +power off cache. Deeper C-states will automatically be restricted on +pseudo-locked region creation. It is required that an application using a pseudo-locked region runs with affinity to the cores (or a subset of the cores) associated |