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authorLinus Torvalds <torvalds@linux-foundation.org>2016-10-22 10:23:15 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2016-10-22 10:23:15 -0700
commit0c2b6dc4fd4fa13796b319aae969a009f03222c6 (patch)
tree82800291c44976174d561ce95914a214dc8b10b9 /Documentation
parentMerge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip (diff)
parentRevert "clocksource/drivers/timer_sun5i: Replace code by clocksource_mmio_init" (diff)
downloadlinux-dev-0c2b6dc4fd4fa13796b319aae969a009f03222c6.tar.xz
linux-dev-0c2b6dc4fd4fa13796b319aae969a009f03222c6.zip
Merge branch 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull timer updates from Thomas Gleixner: "This updates contains: - A revert which addresses a boot failure on ARM Sun5i platforms - A new clocksource driver, which has been delayed beyond rc1 due to an interrupt driver issue which was unearthed by this driver. The debugging of that issue and the discussion about the proper solution made this driver miss the merge window. There is no point in delaying it for a full cycle as it completes the basic mainline support for the new JCore platform and does not create any risk outside of that platform" * 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: Revert "clocksource/drivers/timer_sun5i: Replace code by clocksource_mmio_init" clocksource: Add J-Core timer/clocksource driver of: Add J-Core timer bindings
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/timer/jcore,pit.txt24
1 files changed, 24 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt
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+++ b/Documentation/devicetree/bindings/timer/jcore,pit.txt
@@ -0,0 +1,24 @@
+J-Core Programmable Interval Timer and Clocksource
+
+Required properties:
+
+- compatible: Must be "jcore,pit".
+
+- reg: Memory region(s) for timer/clocksource registers. For SMP,
+ there should be one region per cpu, indexed by the sequential,
+ zero-based hardware cpu number.
+
+- interrupts: An interrupt to assign for the timer. The actual pit
+ core is integrated with the aic and allows the timer interrupt
+ assignment to be programmed by software, but this property is
+ required in order to reserve an interrupt number that doesn't
+ conflict with other devices.
+
+
+Example:
+
+timer@200 {
+ compatible = "jcore,pit";
+ reg = < 0x200 0x30 0x500 0x30 >;
+ interrupts = < 0x48 >;
+};