aboutsummaryrefslogtreecommitdiffstats
path: root/Documentation
diff options
context:
space:
mode:
authorMark Brown <broonie@kernel.org>2015-02-09 15:10:02 +0800
committerMark Brown <broonie@kernel.org>2015-02-09 15:10:02 +0800
commit103004749235915190b81108f6bf4dbf53f220b9 (patch)
treed15f43ad6a9ecb7e4815e86d4aceef671d1d1df7 /Documentation
parentMerge remote-tracking branch 'asoc/topic/dmaengine' into asoc-next (diff)
parentASoC: pcm512x: Use the correct range constraints for S24_LE (diff)
downloadlinux-dev-103004749235915190b81108f6bf4dbf53f220b9.tar.xz
linux-dev-103004749235915190b81108f6bf4dbf53f220b9.zip
Merge remote-tracking branch 'asoc/topic/pcm512x' into asoc-next
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/sound/pcm512x.txt25
1 files changed, 23 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/sound/pcm512x.txt b/Documentation/devicetree/bindings/sound/pcm512x.txt
index 98e0d34915e8..3aae3b41bd8e 100644
--- a/Documentation/devicetree/bindings/sound/pcm512x.txt
+++ b/Documentation/devicetree/bindings/sound/pcm512x.txt
@@ -17,9 +17,16 @@ Required properties:
Optional properties:
- clocks : A clock specifier for the clock connected as SCLK. If this
- is absent the device will be configured to clock from BCLK.
+ is absent the device will be configured to clock from BCLK. If pll-in
+ and pll-out are specified in addition to a clock, the device is
+ configured to accept clock input on a specified gpio pin.
-Example:
+ - pll-in, pll-out : gpio pins used to connect the pll using <1>
+ through <6>. The device will be configured for clock input on the
+ given pll-in pin and PLL output on the given pll-out pin. An
+ external connection from the pll-out pin to the SCLK pin is assumed.
+
+Examples:
pcm5122: pcm5122@4c {
compatible = "ti,pcm5122";
@@ -29,3 +36,17 @@ Example:
DVDD-supply = <&reg_1v8>;
CPVDD-supply = <&reg_3v3>;
};
+
+
+ pcm5142: pcm5142@4c {
+ compatible = "ti,pcm5142";
+ reg = <0x4c>;
+
+ AVDD-supply = <&reg_3v3_analog>;
+ DVDD-supply = <&reg_1v8>;
+ CPVDD-supply = <&reg_3v3>;
+
+ clocks = <&sck>;
+ pll-in = <3>;
+ pll-out = <6>;
+ };