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| author |   Philippe Bergheaud <felix@linux.ibm.com> | 2018-05-14 10:27:36 +0200 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2018-05-15 21:30:01 +1000 |
| commit | 497a0790e2c604366b9e35dcb41310319e9bca13 (patch) | |
| tree | 4e2d24aa965a94a434daeeebf6ae02befc66fdd9 /Documentation | |
| parent | cxl: Set the PBCQ Tunnel BAR register when enabling capi mode (diff) | |
| download | linux-dev-497a0790e2c604366b9e35dcb41310319e9bca13.tar.xz linux-dev-497a0790e2c604366b9e35dcb41310319e9bca13.zip | |
cxl: Report the tunneled operations status
Failure to synchronize the tunneled operations does not prevent
the initialization of the cxl card. This patch reports the tunneled
operations status via /sys.
Signed-off-by: Philippe Bergheaud <felix@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/ABI/testing/sysfs-class-cxl | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/ABI/testing/sysfs-class-cxl b/Documentation/ABI/testing/sysfs-class-cxl index 640f65e79ef1..8e69345c37cc 100644 --- a/Documentation/ABI/testing/sysfs-class-cxl +++ b/Documentation/ABI/testing/sysfs-class-cxl @@ -244,3 +244,11 @@ Description: read only Returns 1 if the psl timebase register is synchronized with the core timebase register, 0 otherwise. Users: https://github.com/ibm-capi/libcxl + +What: /sys/class/cxl/<card>/tunneled_ops_supported +Date: May 2018 +Contact: linuxppc-dev@lists.ozlabs.org +Description: read only + Returns 1 if tunneled operations are supported in capi mode, + 0 otherwise. +Users: https://github.com/ibm-capi/libcxl |