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authorLudovic Desroches <ludovic.desroches@atmel.com>2013-06-13 10:39:38 +0200
committerVinod Koul <vinod.koul@intel.com>2013-07-05 11:40:53 +0530
commit764037c6f55c5c844d0ab6049e6e7c0dc3cb7665 (patch)
tree58e1f14c501d25fa1d1df6df45a723d6fd33cd6e /Documentation
parentMIPS: jz4740: Correct clock gate bit for DMA controller (diff)
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ARM: at91: dt: add header to define at_hdmac configuration
DMA-cell content is a concatenation of several values. In order to keep this stuff human readable, macros are introduced. The values for the FIFO configuration are not the same as the ones used in the configuration register in order to keep backward compatibility. Most devices use the half FIFO configuration but USART ones have to use the ASAP configuration. This parameter was not initially planed to be into the at91 dma dt binding. The third cell will be used to store this parameter, it will become a concatenation of the FIFO configuration and of the peripheral ID. In order to keep backward compatibility i.e. FIFO configuration is equal to 0, we have to perform a translation since the value to put in the register to set half FIFO is 1. Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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