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authorMoritz Fischer <mdf@kernel.org>2019-02-04 09:30:38 -0800
committerDavid S. Miller <davem@davemloft.net>2019-02-05 10:34:34 -0800
commitdd648818dad3ad5ab5151c7f5ca0bb55a0bf71de (patch)
treedd183c09bab2ce91f812b204525ea5e011cb0c6e /Documentation
parentnet: phy: fixed-phy: Drop GPIO from fixed_phy_add() (diff)
downloadlinux-dev-dd648818dad3ad5ab5151c7f5ca0bb55a0bf71de.tar.xz
linux-dev-dd648818dad3ad5ab5151c7f5ca0bb55a0bf71de.zip
net: nixge: Make mdio child node optional
Make MDIO child optional and only instantiate the MDIO bus if the child is actually present. There are currently no (in-tree) users of this binding; all (out-of-tree) users use overlays that get shipped together with the FPGA images that contain the IP. This will significantly increase maintainabilty of future revisions of this IP. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/net/nixge.txt27
1 files changed, 24 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/net/nixge.txt b/Documentation/devicetree/bindings/net/nixge.txt
index 44a7358b4399..bb2929f9c64f 100644
--- a/Documentation/devicetree/bindings/net/nixge.txt
+++ b/Documentation/devicetree/bindings/net/nixge.txt
@@ -16,6 +16,9 @@ Required properties:
- nvmem-cells: Phandle of nvmem cell containing the MAC address
- nvmem-cell-names: Should be "address"
+Optional properties:
+- mdio subnode to indicate presence of MDIO controller
+
Examples (10G generic PHY):
nixge0: ethernet@40000000 {
compatible = "ni,xge-enet-3.00";
@@ -33,8 +36,26 @@ Examples (10G generic PHY):
phy-mode = "xgmii";
phy-handle = <&ethernet_phy1>;
- ethernet_phy1: ethernet-phy@4 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <4>;
+ mdio {
+ ethernet_phy1: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <4>;
+ };
};
};
+
+Examples (10G generic PHY, no MDIO):
+ nixge0: ethernet@40000000 {
+ compatible = "ni,xge-enet-2.00";
+ reg = <0x40000000 0x6000>;
+
+ nvmem-cells = <&eth1_addr>;
+ nvmem-cell-names = "address";
+
+ interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rx", "tx";
+ interrupt-parent = <&intc>;
+
+ phy-mode = "xgmii";
+ phy-handle = <&ethernet_phy1>;
+ };