path: root/Documentation
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authorKrzysztof Kozlowski <k.kozlowski@samsung.com>2014-12-05 15:15:34 +0100
committerMichael Turquette <mturquette@linaro.org>2014-12-17 07:31:51 -0800
commitf1e9203e2366164b832d8a6ce10134de8c575178 (patch)
treeb63f8a883579d364856014b7b122fb0fbc581d5f /Documentation
parentARM: OMAP3: clock: fix boot breakage in legacy mode (diff)
clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated
Audio subsystem clocks are located in separate block. On Exynos 5420 if clock for this block (from main clock domain) 'mau_epll' is gated then any read or write to audss registers will block. This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit after introducing runtime PM to pl330 DMA driver. After that commit the 'mau_epll' was gated, because the "amba" clock was disabled and there were no more users of mau_epll. The system hang on one of steps: 1. Disabling unused clocks from audss block. 2. During audss GPIO setup (just before probing i2s0 because samsung_pinmux_setup() tried to access memory from audss block which was gated. Add a workaround for this by enabling the 'mau_epll' clock in probe. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
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