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authorConor Dooley <conor.dooley@microchip.com>2022-10-10 23:17:05 +0100
committerPalmer Dabbelt <palmer@rivosinc.com>2022-10-11 12:39:14 -0700
commitabbb388d335f8c400d1baecb15d360fa0062de77 (patch)
tree2c21b91c5b0502cfcfd79113d7283b9bfb4fdb4f /MAINTAINERS
parentMAINTAINERS: update polarfire soc clock binding (diff)
downloadlinux-dev-abbb388d335f8c400d1baecb15d360fa0062de77.tar.xz
linux-dev-abbb388d335f8c400d1baecb15d360fa0062de77.zip
dt-bindings: riscv: update microchip.yaml's maintainership
Daire and I are the platform maintainers for Microchip's RISC-V FPGAs. Update the maintainers in microchip.yaml to reflect this and explicitly add the binding to the SoC's MAINTAINERS entry. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20221010221704.2161221-3-conor@kernel.org/ Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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diff --git a/MAINTAINERS b/MAINTAINERS
index 94cf47ea5f80..b3415857a812 100644
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@@ -17651,6 +17651,7 @@ F: Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml
F: Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
F: Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml
F: Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
+F: Documentation/devicetree/bindings/riscv/microchip.yaml
F: Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
F: Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
F: Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml