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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2018-06-15 20:44:06 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2018-06-19 17:18:24 +0300 |
| commit | ad193bc6206d3ee2fc39fe29a2525333faf1afd9 (patch) | |
| tree | b63227be649abfabe32d4daa6a9b474d27d0d2d3 /MAINTAINERS | |
| parent | drm/i915: Check timings against hardware maximums (diff) | |
| download | linux-dev-ad193bc6206d3ee2fc39fe29a2525333faf1afd9.tar.xz linux-dev-ad193bc6206d3ee2fc39fe29a2525333faf1afd9.zip | |
drm/i915: Enforce max hdisplay/hblank_start limits on HSW/BDW FDI
The PCH transcoder registers are only 12 bits wide for the hdisplay
and hblank_start values. On HSW/BDW the CPU side registers are 13
bits wide. intel_mode_valid() only checks against the higher limit
(since we don't know where the mode is to be used), so an extra
check is required against the FDI limits.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180615174406.12258-3-ville.syrjala@linux.intel.com
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Diffstat (limited to 'MAINTAINERS')
0 files changed, 0 insertions, 0 deletions