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authorArd Biesheuvel <ard.biesheuvel@linaro.org>2017-07-24 11:28:16 +0100
committerHerbert Xu <herbert@gondor.apana.org.au>2017-08-04 09:27:23 +0800
commit537c1445ab0b1e33ca338b669e347652c45f4e8c (patch)
tree0d84da1538a5ef83cf48199ddd97bdb9e3871d8d /arch/alpha
parentcrypto: arm64/aes-bs - implement non-SIMD fallback for AES-CTR (diff)
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crypto: arm64/gcm - implement native driver using v8 Crypto Extensions
Currently, the AES-GCM implementation for arm64 systems that support the ARMv8 Crypto Extensions is based on the generic GCM module, which combines the AES-CTR implementation using AES instructions with the PMULL based GHASH driver. This is suboptimal, given the fact that the input data needs to be loaded twice, once for the encryption and again for the MAC calculation. On Cortex-A57 (r1p2) and other recent cores that implement micro-op fusing for the AES instructions, AES executes at less than 1 cycle per byte, which means that any cycles wasted on loading the data twice hurt even more. So implement a new GCM driver that combines the AES and PMULL instructions at the block level. This improves performance on Cortex-A57 by ~37% (from 3.5 cpb to 2.6 cpb) Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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