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| author |   Vineet Gupta <vgupta@synopsys.com> | 2015-04-06 17:23:57 +0530 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2015-06-22 14:06:55 +0530 |
| commit | d1f317d8254413447bcd6b6adbde24a985d256c2 (patch) | |
| tree | 4b0ba3c3a5335e844edbf97403c12b88b04f69d5 /arch/arc/Kconfig | |
| parent | ARCv2: MMUv4: TLB programming Model changes (diff) | |
| download | linux-dev-d1f317d8254413447bcd6b6adbde24a985d256c2.tar.xz linux-dev-d1f317d8254413447bcd6b6adbde24a985d256c2.zip | |
ARCv2: MMUv4: cache programming model changes
Caveats about cache flush on ARCv2 based cores
- dcache is PIPT so paddr is sufficient for cache maintenance ops (no
need to setup PTAG reg
- icache is still VIPT but only aliasing configs need PTAG setup
So basically this is departure from MMU-v3 which always need vaddr in
line ops registers (DC_IVDL, DC_FLDL, IC_IVIL) but paddr in DC_PTAG,
IC_PTAG respectively.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/Kconfig')
| -rw-r--r-- | arch/arc/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 6568977bb302..974ed9058018 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -223,7 +223,7 @@ config ARC_CACHE_PAGES config ARC_CACHE_VIPT_ALIASING bool "Support VIPT Aliasing D$" - depends on ARC_HAS_DCACHE + depends on ARC_HAS_DCACHE && ISA_ARCOMPACT default n endif #ARC_CACHE |