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| author |   Linus Torvalds <torvalds@linux-foundation.org> | 2016-12-23 10:22:47 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2016-12-23 10:22:47 -0800 |
| commit | 42e0372c0e7ea3617a4ab28c7f83ce66cb0f868d (patch) | |
| tree | f6b94f1baaa27270d9c7c76256cb67aa4df0597e /arch/arc/include | |
| parent | Merge tag 'leds_for_4.10_email_update' of git://git.kernel.org/pub/scm/linux/kernel/git/j.anaszewski/linux-leds (diff) | |
| parent | ARC: mm: arc700: Don't assume 2 colours for aliasing VIPT dcache (diff) | |
| download | linux-dev-42e0372c0e7ea3617a4ab28c7f83ce66cb0f868d.tar.xz linux-dev-42e0372c0e7ea3617a4ab28c7f83ce66cb0f868d.zip | |
Merge tag 'arc-4.10-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull more ARC updates from Vineet Gupta:
- Fix for aliasing VIPT dcache in old ARC700 cores
- micro-optimization in ARC700 ProtV handler
- Enable SG_CHAIN [Vladimir]
- ARC HS38 core intc default to prio 1
* tag 'arc-4.10-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
ARC: mm: arc700: Don't assume 2 colours for aliasing VIPT dcache
ARC: mm: No need to save cache version in @cpuinfo
ARC: enable SG chaining
ARCv2: intc: default all interrupts to priority 1
ARCv2: entry: document intr disable in hard isr
ARC: ARCompact entry: elide re-reading ECR in ProtV handler
Diffstat (limited to 'arch/arc/include')
| -rw-r--r-- | arch/arc/include/asm/arcregs.h | 2 | ||||
| -rw-r--r-- | arch/arc/include/asm/cacheflush.h | 6 | ||||
| -rw-r--r-- | arch/arc/include/asm/irqflags-arcv2.h | 6 |
3 files changed, 8 insertions, 6 deletions
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index da41a54ea2d7..f659942744de 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -244,7 +244,7 @@ struct cpuinfo_arc_mmu { }; struct cpuinfo_arc_cache { - unsigned int sz_k:14, line_len:8, assoc:4, ver:4, alias:1, vipt:1; + unsigned int sz_k:14, line_len:8, assoc:4, alias:1, vipt:1, pad:4; }; struct cpuinfo_arc_bpu { diff --git a/arch/arc/include/asm/cacheflush.h b/arch/arc/include/asm/cacheflush.h index a093adbdb017..fc662f49c55a 100644 --- a/arch/arc/include/asm/cacheflush.h +++ b/arch/arc/include/asm/cacheflush.h @@ -85,6 +85,10 @@ void flush_anon_page(struct vm_area_struct *vma, */ #define PG_dc_clean PG_arch_1 +#define CACHE_COLORS_NUM 4 +#define CACHE_COLORS_MSK (CACHE_COLORS_NUM - 1) +#define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & CACHE_COLORS_MSK) + /* * Simple wrapper over config option * Bootup code ensures that hardware matches kernel configuration @@ -94,8 +98,6 @@ static inline int cache_is_vipt_aliasing(void) return IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING); } -#define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & 1) - /* * checks if two addresses (after page aligning) index into same cache set */ diff --git a/arch/arc/include/asm/irqflags-arcv2.h b/arch/arc/include/asm/irqflags-arcv2.h index e880dfa3fcd3..a64c447b0337 100644 --- a/arch/arc/include/asm/irqflags-arcv2.h +++ b/arch/arc/include/asm/irqflags-arcv2.h @@ -38,10 +38,10 @@ #define AUX_IRQ_ACT_BIT_U 31 /* - * User space should be interruptable even by lowest prio interrupt - * Safe even if actual interrupt priorities is fewer or even one + * Hardware supports 16 priorities (0 highest, 15 lowest) + * Linux by default runs at 1, priority 0 reserved for NMI style interrupts */ -#define ARCV2_IRQ_DEF_PRIO 15 +#define ARCV2_IRQ_DEF_PRIO 1 /* seed value for status register */ #define ISA_INIT_STATUS_BITS (STATUS_IE_MASK | STATUS_AD_MASK | \ |