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authorVineet Gupta <vgupta@synopsys.com>2013-09-18 16:25:40 +0530
committerVineet Gupta <vgupta@synopsys.com>2013-11-06 10:41:39 +0530
commit21a63b56044706aa37637315dd27d9d465bbd5c4 (patch)
treec92bbd890472c22c99b89dd0749a117c7ca0a51e /arch/arc/kernel/entry.S
parentARC: cacheflush optim - PTAG can be loop invariant if V-P is const (diff)
downloadlinux-dev-21a63b56044706aa37637315dd27d9d465bbd5c4.tar.xz
linux-dev-21a63b56044706aa37637315dd27d9d465bbd5c4.zip
ARC: Change calling convention of do_page_fault()
switch the args (address, pt_regs) to match with all the other "C" exception handlers. This removes the awkwardness in EV_ProtV for page fault vs. unaligned access. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/kernel/entry.S')
-rw-r--r--arch/arc/kernel/entry.S9
1 files changed, 4 insertions, 5 deletions
diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S
index b908dde8a331..eb3f3c5a700a 100644
--- a/arch/arc/kernel/entry.S
+++ b/arch/arc/kernel/entry.S
@@ -337,9 +337,9 @@ ARC_ENTRY EV_TLBProtV
; vineetg: Mar 6th: Random Seg Fault issue #1
; ecr and efa were not saved in case an Intr sneaks in
; after fake rtie
- ;
+
lr r2, [ecr]
- lr r1, [efa] ; Faulting Data address
+ lr r0, [efa] ; Faulting Data address
; --------(4) Return from CPU Exception Mode ---------
; Fake a rtie, but rtie to next label
@@ -348,6 +348,8 @@ ARC_ENTRY EV_TLBProtV
FAKE_RET_FROM_EXCPN r9
+ mov r1, sp
+
;------ (5) Type of Protection Violation? ----------
;
; ProtV Hardware Exception is triggered for Access Faults of 2 types
@@ -358,14 +360,11 @@ ARC_ENTRY EV_TLBProtV
bbit1 r2, ECR_C_BIT_PROTV_MISALIG_DATA, 4f
;========= (6a) Access Violation Processing ========
- mov r0, sp ; pt_regs
bl do_page_fault
b ret_from_exception
;========== (6b) Non aligned access ============
4:
- mov r0, r1
- mov r1, sp ; pt_regs
#ifdef CONFIG_ARC_MISALIGN_ACCESS
SAVE_CALLEE_SAVED_USER