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| author |   Jason A. Donenfeld <Jason@zx2c4.com> | 2018-10-02 15:01:24 +0100 |
|---|---|---|
| committer |   Russell King <rmk+kernel@armlinux.org.uk> | 2018-10-04 14:48:59 +0100 |
| commit | 8403bcb779a0be4080510c59b1a582e6ab7a748c (patch) | |
| tree | 98336755cac0cf00e7d94cfd724f9c2605aca144 /arch/arm/Makefile | |
| parent | ARM: 8800/1: use choice for kernel unwinders (diff) | |
| download | linux-dev-8403bcb779a0be4080510c59b1a582e6ab7a748c.tar.xz linux-dev-8403bcb779a0be4080510c59b1a582e6ab7a748c.zip | |
ARM: 8801/1: makefile: use ARMv3M mode for RiscPC
The purpose of CONFIG_CPU_32v3 is to avoid ldrh/strh on the RiscPC,
which is pretty much an ARMv4 device, except its bus will choke on the
half-words. The way to make the C compiler not output ldrh/strh is with
-march=armv3, which doesn't support them in the ISA. However, this
prevents certain cryptography code from working that uses instructions
like umull. Fortunately there's also -march=armv3m that does support
those, making it possible to continue assembling optimized cryptography
routines for our beloved RiscPC.
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch/arm/Makefile')
| -rw-r--r-- | arch/arm/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 06ebff73273f..5c91e0093ee8 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -74,7 +74,7 @@ endif arch-$(CONFIG_CPU_32v5) =-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4t) arch-$(CONFIG_CPU_32v4T) =-D__LINUX_ARM_ARCH__=4 -march=armv4t arch-$(CONFIG_CPU_32v4) =-D__LINUX_ARM_ARCH__=4 -march=armv4 -arch-$(CONFIG_CPU_32v3) =-D__LINUX_ARM_ARCH__=3 -march=armv3 +arch-$(CONFIG_CPU_32v3) =-D__LINUX_ARM_ARCH__=3 -march=armv3m # Evaluate arch cc-option calls now arch-y := $(arch-y) |