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| author |   Ard Biesheuvel <ardb@kernel.org> | 2020-10-03 17:28:27 +0200 |
|---|---|---|
| committer | Ard Biesheuvel <ardb@kernel.org> | 2020-10-26 08:02:11 +0100 |
| commit | fbc81ec5b85d43a4b22e49ec0e643fa7dec2ea40 (patch) | |
| tree | 8b99a6ce15a9b0bfc96db687eb6e79418e2c620d /arch/arm/boot/compressed | |
| parent | Linux 5.10-rc1 (diff) | |
| download | linux-dev-fbc81ec5b85d43a4b22e49ec0e643fa7dec2ea40.tar.xz linux-dev-fbc81ec5b85d43a4b22e49ec0e643fa7dec2ea40.zip | |
efi/arm: set HSCTLR Thumb2 bit correctly for HVC calls from HYP
Commit
db227c19e68db353 ("ARM: 8985/1: efi/decompressor: deal with HYP mode boot gracefully")
updated the EFI entry code to permit firmware to invoke the EFI stub
loader in HYP mode, with the MMU either enabled or disabled, neither
of which is permitted by the EFI spec, but which does happen in the
field.
In the MMU on case, we remain in HYP mode as configured by the firmware,
and rely on the fact that any HVC instruction issued in this mode will
be dispatched via the SVC slot in the HYP vector table. However, this
slot will point to a Thumb2 symbol if the kernel is built in Thumb2
mode, and so we have to configure HSCTLR to ensure that the exception
handlers are invoked in Thumb2 mode as well.
Fixes: db227c19e68db353 ("ARM: 8985/1: efi/decompressor: deal with HYP mode boot gracefully")
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Diffstat (limited to 'arch/arm/boot/compressed')
| -rw-r--r-- | arch/arm/boot/compressed/head.S | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 2e04ec5b5446..caa27322a0ab 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -1472,6 +1472,9 @@ ENTRY(efi_enter_kernel) @ issued from HYP mode take us to the correct handler code. We @ will disable the MMU before jumping to the kernel proper. @ + ARM( bic r1, r1, #(1 << 30) ) @ clear HSCTLR.TE + THUMB( orr r1, r1, #(1 << 30) ) @ set HSCTLR.TE + mcr p15, 4, r1, c1, c0, 0 adr r0, __hyp_reentry_vectors mcr p15, 4, r0, c12, c0, 0 @ set HYP vector base (HVBAR) isb |