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| author |   Tero Kristo <t-kristo@ti.com> | 2020-04-29 17:30:02 +0300 |
|---|---|---|
| committer |   Tony Lindgren <tony@atomide.com> | 2020-05-05 11:16:06 -0700 |
| commit | e88ba436e5615f5bb94deecbbb924227b15bbebb (patch) | |
| tree | 3c8d5b8cd4c9cf711b2be87b38d1e8a99fb6ec2c /arch/arm/boot/dts/am33xx.dtsi | |
| parent | ARM: OMAP4: Make L4SEC clock domain SWSUP only (diff) | |
| download | linux-dev-e88ba436e5615f5bb94deecbbb924227b15bbebb.tar.xz linux-dev-e88ba436e5615f5bb94deecbbb924227b15bbebb.zip | |
ARM: OMAP5: Make L4SEC clock domain SWSUP only
Commit c2ce5fb3f3f5 ('ARM: OMAP: DRA7xx: Make L4SEC clock domain SWSUP
only') made DRA7 SoC L4SEC clock domain SWSUP only because of power
state transition issues detected with HWSUP mode. Based on
experimentation similar issue exists on OMAP5, so do the same change
for OMAP5 also.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/am33xx.dtsi')
0 files changed, 0 insertions, 0 deletions