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| author |   Chia-Wei Wang <chiawei_wang@aspeedtech.com> | 2021-09-27 10:30:53 +0800 |
|---|---|---|
| committer |   Joel Stanley <joel@jms.id.au> | 2021-10-21 16:59:53 +1030 |
| commit | f9241fe8b9652e6751f4ae684efe0148e3c157c7 (patch) | |
| tree | 5a38eedb61528e2534e5d4ec5b7685682baacb10 /arch/arm/boot/dts/aspeed-g6.dtsi | |
| parent | ARM: dts: aspeed: rainier: Enable earlycon (diff) | |
| download | linux-dev-f9241fe8b9652e6751f4ae684efe0148e3c157c7.tar.xz linux-dev-f9241fe8b9652e6751f4ae684efe0148e3c157c7.zip | |
ARM: dts: aspeed: Add uart routing to device tree
Add LPC uart routing to the device tree for Aspeed SoCs.
Signed-off-by: Oskar Senft <osk@google.com>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Tested-by: Lei YU <yulei.sh@bytedance.com>
Link: https://lore.kernel.org/r/20210927023053.6728-6-chiawei_wang@aspeedtech.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Diffstat (limited to 'arch/arm/boot/dts/aspeed-g6.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/aspeed-g6.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index ee171b3364fa..5106a424f1ce 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -571,6 +571,12 @@ #reset-cells = <1>; }; + uart_routing: uart-routing@98 { + compatible = "aspeed,ast2600-uart-routing"; + reg = <0x98 0x8>; + status = "disabled"; + }; + ibt: ibt@140 { compatible = "aspeed,ast2600-ibt-bmc"; reg = <0x140 0x18>; |