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| author |   Roger Quadros <rogerq@ti.com> | 2020-03-13 11:47:17 +0200 |
|---|---|---|
| committer |   Tony Lindgren <tony@atomide.com> | 2020-03-13 07:40:55 -0700 |
| commit | cfb5d65f25959f724081bae8445a0241db606af6 (patch) | |
| tree | f17a02ea49e4c3be21e48deda0191a777e51c039 /arch/arm/boot/dts/dra7.dtsi | |
| parent | Merge branch 'fix-lcdc-quirk' into fixes (diff) | |
| download | linux-dev-cfb5d65f25959f724081bae8445a0241db606af6.tar.xz linux-dev-cfb5d65f25959f724081bae8445a0241db606af6.zip | |
ARM: dts: dra7: Add bus_dma_limit for L3 bus
The L3 interconnect's memory map is from 0x0 to
0xffffffff. Out of this, System memory (SDRAM) can be
accessed from 0x80000000 to 0xffffffff (2GB)
DRA7 does support 4GB of SDRAM but upper 2GB can only be
accessed by the MPU subsystem.
Add the dma-ranges property to reflect the physical address limit
of the L3 bus.
Issues ere observed only with SATA on DRA7-EVM with 4GB RAM
and CONFIG_ARM_LPAE enabled. This is because the controller
supports 64-bit DMA and its driver sets the dma_mask to 64-bit
thus resulting in DMA accesses beyond L3 limit of 2G.
Setting the correct bus_dma_limit fixes the issue.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Cc: stable@kernel.org
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/dra7.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/dra7.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 4305051bb769..5f5ee16f07a3 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -148,6 +148,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0xc0000000>; + dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; ti,hwmods = "l3_main_1", "l3_main_2"; reg = <0x0 0x44000000 0x0 0x1000000>, <0x0 0x45000000 0x0 0x1000>; |