Merge tag 'imx-dt-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt

Pull "i.MX device tree updates for 4.14" from Shawn Guo:
 - A series from Andrew Lunn updating imx6-rdu2 board to enable
   on-board Marvell switch support.
 - A series from Jagan Teki updating imx6ul-isiot and imx6ul-geam to
   enable audio card and FEC support.
 - Add support for Toradex Ixora V1.1 and Apalis Evaluation Board
   along with some cleanups.
 - Enable DRM display support for imx6ul-evk and imx7d-sdb board.
 - Add i.MX53 based Beckhoff CX9020 board support.
 - Add GPMI NAND and APBH DMA devices for i.MX7 and enables NAND support
   for imx7-colibri board.
 - Enables the ADV7180 analog video decoder sensor connected to the
   IMX6 IPU on various Gateworks Ventana boards.
 - Minor updates on misc boards and some random cleanups.

* tag 'imx-dt-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (47 commits)
  ARM: dts: imx6q-bx50v3: Enable i2c recovery mechanism
  ARM: dts: imx6q-apalis-eval: add support for Apalis Evaluation Board
  ARM: dts: imx6: add support for Toradex Ixora V1.1 carrier board
  ARM: dts: imx6qdl-apalis: imx6q-apalis-ixora: use i2c from dwc hdmi
  ARM: dts: imx6q-apalis-ixora: add camera i2c bus definition
  ARM: dts: imx6q-apalis-ixora: get rid of obsolete fusion comment
  ARM: dts: imx6qdl-apalis: reword cam i2c comment
  ARM: dts: imx6qdl-apalis: imx6q-apalis-ixora: get rid of tegra legacy gen1_i2c comment
  ARM: dts: imx6q-apalis-ixora: combine aliases
  ARM: dts: imx6qdl-apalis: split usdhc1 pinctrl to support 4- and 8-bit
  ARM: dts: imx6q-apalis-ixora: fix usdhc2 pinctrl property
  ARM: dts: imx6ul-liteboard: Support poweroff
  ARM: dts: imx: add CX9020 Embedded PC device tree
  ARM: dts: imx53: add alternative UART2 configuration
  ARM: dts: imx53: add srtc node
  dt-bindings: arm: Add entry for Beckhoff CX9020
  ARM: dts: i.MX25: add RNGB node to dtsi
  ARM: dts: imx6ul-14x14-evk: Remove unrelated pin from ENET group
  ARM: dts: imx7d-sdb: Add flexcan support
  ARM: dts: imx7-colibri: add NAND support
  ...

1 files changed, 54 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
index e8c1edc82e6e..885556260bd0 100644
--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -231,6 +231,37 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_i2c3>;
 	status = "okay";
+
+	adv7180: camera@20 {
+		compatible = "adi,adv7180";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_adv7180>;
+		reg = <0x20>;
+		powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+
+		port {
+			adv7180_to_ipu1_csi0_mux: endpoint {
+				remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+				bus-width = <8>;
+			};
+		};
+	};
+};
+
+&ipu1_csi0_from_ipu1_csi0_mux {
+	bus-width = <8>;
+};
+
+&ipu1_csi0_mux_from_parallel_sensor {
+	remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
+	bus-width = <8>;
+};
+
+&ipu1_csi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ipu1_csi0>;
 };
 
 &pcie {
@@ -302,6 +333,13 @@
 
 &iomuxc {
 	imx6qdl-gw51xx {
+		pinctrl_adv7180: adv7180grp {
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23        0x0001b0b0
+				MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20     0x4001b0b0
+			>;
+		};
+
 		pinctrl_enet: enetgrp {
 			fsl,pins = <
 				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
@@ -372,6 +410,22 @@
 			>;
 		};
 
+		pinctrl_ipu1_csi0: ipu1csi0grp {
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x1b0b0
+				MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x1b0b0
+				MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x1b0b0
+				MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x1b0b0
+				MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x1b0b0
+				MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x1b0b0
+				MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x1b0b0
+				MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x1b0b0
+				MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x1b0b0
+				MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x1b0b0
+				MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x1b0b0
+			>;
+		};
+
 		pinctrl_pcie: pciegrp {
 			fsl,pins = <
 				MX6QDL_PAD_GPIO_0__GPIO1_IO00		0x1b0b0