diff options
| author |   Peter Seiderer <ps.report@gmx.net> | 2015-06-02 21:07:17 +0200 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2015-07-15 10:20:33 +0800 |
| commit | 366c595f1381b89c52153f753a6499c349410a02 (patch) | |
| tree | a8d5e2c5f628457b3175a41d67382d8dce04c71a /arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | |
| parent | ARM: dts: nitrogen6x: add CAN support (diff) | |
| download | linux-dev-366c595f1381b89c52153f753a6499c349410a02.tar.xz linux-dev-366c595f1381b89c52153f753a6499c349410a02.zip | |
ARM: dts: sabrelite: add CAN support
Signed-off-by: Peter Seiderer <ps.report@gmx.net>
Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-sabrelite.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index e00c44f6a0df..fe010590fda2 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -53,6 +53,17 @@ gpio = <&gpio3 22 0>; enable-active-high; }; + + reg_can_xcvr: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_xcvr>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; }; gpio-keys { @@ -148,6 +159,13 @@ status = "okay"; }; +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; +}; + &ecspi1 { fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio3 19 0>; @@ -239,6 +257,20 @@ >; }; + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_can_xcvr: can-xcvrgrp { + fsl,pins = < + /* Flexcan XCVR enable */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 |