diff options
| author |   Maciej S. Szmigiero <mail@maciej.szmigiero.name> | 2017-11-20 20:08:30 +0100 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2017-12-26 16:15:44 +0800 |
| commit | 39e0024f5158fecf92a19483f85701c7d04f30b8 (patch) | |
| tree | 22dc8ad85537f753346b5f44ce1b59a2602b7c50 /arch/arm/boot/dts/imx6qdl-udoo.dtsi | |
| parent | ARM: dts: ls1021a: add "fsl,ls1021a-esdhc" compatible string to esdhc node (diff) | |
| download | linux-dev-39e0024f5158fecf92a19483f85701c7d04f30b8.tar.xz linux-dev-39e0024f5158fecf92a19483f85701c7d04f30b8.zip | |
ARM: dts: imx6qdl-udoo: disable AC'97 input pins pad drivers
AC'97 interface RXD and TXC pins are only used as SoC inputs, let's disable
pad drivers for them so we will be protected if, for example, TCLKDIR is
set by mistake in AUDMUX and causes TXC pin to be configured as an output.
This also changes pull direction on these pins from pull-up to pull-down
to match what the board AC'97 CODEC chip (VT1613) has on these pins.
Signed-off-by: Maciej S. Szmigiero <mail@maciej.szmigiero.name>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-udoo.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-udoo.dtsi | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi index c96c91d83678..839282c55701 100644 --- a/arch/arm/boot/dts/imx6qdl-udoo.dtsi +++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi @@ -208,8 +208,8 @@ fsl,pins = < MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x1b0b0 - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x1b0b0 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x1b0b0 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 >; }; @@ -218,8 +218,8 @@ fsl,pins = < MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x1b0b0 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x1b0b0 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 >; }; @@ -228,8 +228,8 @@ fsl,pins = < MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x1b0b0 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x1b0b0 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 >; }; |