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| author |   Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2020-06-20 18:36:52 +0200 |
|---|---|---|
| committer |   Kevin Hilman <khilman@baylibre.com> | 2020-07-13 11:58:15 -0700 |
| commit | 73106f75bf9498ff5d50f1052ad3cf03730d806d (patch) | |
| tree | 3a7a7a0dfc78fafa3846b712703d72d4ebb8ee36 /arch/arm/boot/dts/meson.dtsi | |
| parent | ARM: dts: meson8b: add power domain controller (diff) | |
| download | linux-dev-73106f75bf9498ff5d50f1052ad3cf03730d806d.tar.xz linux-dev-73106f75bf9498ff5d50f1052ad3cf03730d806d.zip | |
ARM: dts: meson: add the SDHC MMC controller
Meson6, Meson8, Meson8b and Meson8m2 are using a similar SDHC controller
IP which typically connects to an eMMC chip (because unlike the SDIO
controller the SDHC controller has an 8-bit bus interface).
On Meson8, Meson8b and Meson8m2 the clock inputs are all the same.
However, Meson8m2 seems to have an improved version of the SHDC
controller IP which doesn't require the driver to wait manually for a
flush of a DMA transfer. Thus every SoC has it's own compatible string
so if more difference are discovered they can be implemented.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200620163654.37207-2-martin.blumenstingl@googlemail.com
Diffstat (limited to 'arch/arm/boot/dts/meson.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/meson.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index ae89deaa8c9c..464057989572 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -140,6 +140,13 @@ status = "disabled"; }; + sdhc: mmc@8e00 { + compatible = "amlogic,meson-mx-sdhc"; + reg = <0x8e00 0x42>; + interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + gpio_intc: interrupt-controller@9880 { compatible = "amlogic,meson-gpio-intc"; reg = <0x9880 0x10>; |