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authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>2018-11-23 20:53:09 +0100
committerKevin Hilman <khilman@baylibre.com>2018-12-04 16:48:13 -0800
commit2710e8d2131047c042b390c26d9a1ad9fe5765a1 (patch)
tree19c976c5dc6b8384ce4e739b148c5f93b43f259b /arch/arm/boot/dts/meson8.dtsi
parentARM: dts: meson8: add the ARM TWD timer (diff)
downloadlinux-dev-2710e8d2131047c042b390c26d9a1ad9fe5765a1.tar.xz
linux-dev-2710e8d2131047c042b390c26d9a1ad9fe5765a1.zip
ARM: dts: meson8: add the Cortex-A9 global timer
The Meson8 and Meson8m2 SoCs are using four Cortex-A9 cores. These come with an ARM global timer. This adds the Cortex-A9 global timer but keeps it disabled for now. The timer is clocked by the "PERIPH" clock whose rate can change during runtime (when changing the frequency of the CPU clock). Unfortunately the arm_global_timer driver does not handle changes to the clock rate yet. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'arch/arm/boot/dts/meson8.dtsi')
-rw-r--r--arch/arm/boot/dts/meson8.dtsi13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 2b0b3edbd896..2575a5835567 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -363,6 +363,19 @@
reg = <0x0 0x100>;
};
+ timer@200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x200 0x20>;
+ interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
+ clocks = <&clkc CLKID_PERIPH>;
+
+ /*
+ * the arm_global_timer driver currently does not handle clock
+ * rate changes. Keep it disabled for now.
+ */
+ status = "disabled";
+ };
+
timer@600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x600 0x20>;