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authorTony Lindgren <tony@atomide.com>2019-12-12 09:46:11 -0800
committerTony Lindgren <tony@atomide.com>2020-01-23 08:23:26 -0800
commitfbb8bb8370f6fdaaaccf85201f4ee2a665aae42d (patch)
treec998a79a631c334e9d11010483a3a021b8732e89 /arch/arm/boot/dts/omap5-l4.dtsi
parentARM: dts: Add missing omap5 secure clocks (diff)
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ARM: dts: Configure omap4 rng to probe with ti-sysc
Add RNG interconnect data for omap4 similar to what dra7 has. The clock is OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET at offset address 0x01c0, which matches what dra7 also has with DRA7_L4SEC_CLKCTRL_INDEX(0x1c0). Note that we need to also add the related l4_secure clock entries. I've only added RNG, the others can be added as they get tested. They are probably very similar to what we already have for dra7 in dra7_l4sec_clkctrl_regs[]. With the clock tagged CLKF_SOC_NONSEC, clock is set disabled for secure devices and clk_get() will fail. Additionally we disable the RNG target module on droid4 to avoid introducing new boot time warnings. Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/omap5-l4.dtsi')
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