diff options
| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2017-08-18 11:11:34 +0200 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2017-09-18 08:05:01 +0200 |
| commit | 5802c420636559ffd37095d2886f6964d9b55b11 (patch) | |
| tree | d3823cdb0f0385c514ca7220f140cc13eb44982f /arch/arm/boot/dts/r8a7790-lager.dts | |
| parent | Linux 4.14-rc1 (diff) | |
| download | linux-dev-5802c420636559ffd37095d2886f6964d9b55b11.tar.xz linux-dev-5802c420636559ffd37095d2886f6964d9b55b11.zip | |
ARM: dts: r8a7790: Convert to new CPG/MSSR bindings
Convert the R-Car H2 SoC from the old "Renesas R-Car Gen2 Clock Pulse
Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop
(MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse
Generator / Module Standby and Software Reset" DT bindings.
This simplifies the DTS files, and allows to add support for reset
control later.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7790-lager.dts')
| -rw-r--r-- | arch/arm/boot/dts/r8a7790-lager.dts | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index ba100a6f67ca..e3d27783b6b5 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -316,11 +316,8 @@ pinctrl-names = "default"; status = "okay"; - clocks = <&mstp7_clks R8A7790_CLK_DU0>, - <&mstp7_clks R8A7790_CLK_DU1>, - <&mstp7_clks R8A7790_CLK_DU2>, - <&mstp7_clks R8A7790_CLK_LVDS0>, - <&mstp7_clks R8A7790_CLK_LVDS1>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, + <&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>, <&x13_clk>, <&x2_clk>; clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1", "dclkin.0", "dclkin.1"; |