diff options
| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2017-10-12 11:35:10 +0200 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2017-10-16 11:39:31 +0200 |
| commit | aa4c2fdf495f000fa9ae57c073c0c4575c21983e (patch) | |
| tree | e172bf89d3c062b4fcff6a2e8f5b3f63604fada0 /arch/arm/boot/dts/r8a7790.dtsi | |
| parent | ARM: dts: r8a7779: Add clocks for CA9 CPU cores (diff) | |
| download | linux-dev-aa4c2fdf495f000fa9ae57c073c0c4575c21983e.tar.xz linux-dev-aa4c2fdf495f000fa9ae57c073c0c4575c21983e.zip | |
ARM: dts: r8a7790: Add missing clocks for secondary CA15 CPU cores
Currently only the primary CPU in the CA15 cluster has a clocks
property, while the secondary CPU cores are driven by the same clock.
Add the missing clocks properties to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7790.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7790.dtsi | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index f247beb3863f..e85eb42f97e8 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -72,6 +72,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1300000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; @@ -82,6 +83,7 @@ compatible = "arm,cortex-a15"; reg = <2>; clock-frequency = <1300000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU2>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; @@ -92,6 +94,7 @@ compatible = "arm,cortex-a15"; reg = <3>; clock-frequency = <1300000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU3>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; |