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authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>2016-08-26 23:21:42 +0300
committerSimon Horman <horms+renesas@verge.net.au>2016-09-05 14:32:32 +0200
commit5f45cec40402188a269dd56e9a1a569cc4849014 (patch)
tree44d5a22ba028f0e3ee8d1e9272f2f01894e57d42 /arch/arm/boot/dts/r8a7792-wheat.dts
parentARM: dts: document Wheat board (diff)
downloadlinux-dev-5f45cec40402188a269dd56e9a1a569cc4849014.tar.xz
linux-dev-5f45cec40402188a269dd56e9a1a569cc4849014.zip
ARM: dts: wheat: initial device tree
Add the initial device tree for the R8A7792 SoC based Wheat board. The Wheat board itself has no serial ports wired up, the USB serial chips are situated on a separate debug board and one of them is connected to SCFI0 -- include unconditional support for it, so that the serial console can work. Based on the original (and large) patch by Vladimir Barinov <vladimir.barinov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7792-wheat.dts')
-rw-r--r--arch/arm/boot/dts/r8a7792-wheat.dts50
1 files changed, 50 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts
new file mode 100644
index 000000000000..22ae14ffc917
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7792-wheat.dts
@@ -0,0 +1,50 @@
+/*
+ * Device Tree Source for the Wheat board
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation
+ * Copyright (C) 2016 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7792.dtsi"
+
+/ {
+ model = "Wheat";
+ compatible = "renesas,wheat", "renesas,r8a7792";
+
+ aliases {
+ serial0 = &scif0;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
+
+&pfc {
+ scif0_pins: scif0 {
+ groups = "scif0_data";
+ function = "scif0";
+ };
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};