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| author |   Daniel Schultz <d.schultz@phytec.de> | 2018-03-05 13:45:11 +0100 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2018-04-16 14:13:04 +0200 |
| commit | c887f5b0210c5c7d30e2da47c37798eb6f37f563 (patch) | |
| tree | 6a46ca2cf7980f49387ca334b6dce30f5b6d4409 /arch/arm/boot/dts/rk3288-phycore-som.dtsi | |
| parent | ARM: dts: rockchip: fix uart4 pin-numbers for rk3288 (diff) | |
| download | linux-dev-c887f5b0210c5c7d30e2da47c37798eb6f37f563.tar.xz linux-dev-c887f5b0210c5c7d30e2da47c37798eb6f37f563.zip | |
ARM: dts: rockchip: Add dp83867 CLK_OUT muxing on rk3288-phycore-som
The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz.
Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rk3288-phycore-som.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/rk3288-phycore-som.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi index f13bcb1cd3d9..aaab2d171ffe 100644 --- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi +++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi @@ -151,6 +151,7 @@ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; enet-phy-lane-no-swap; + ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>; }; }; }; |