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| author |   Dinh Nguyen <dinguyen@kernel.org> | 2018-07-09 17:16:00 -0500 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2018-08-30 08:38:26 -0500 |
| commit | 0ffc5df823dd3495441c47ea3ffaa09d4a57a5f1 (patch) | |
| tree | 69b2f5a5295dec4d8057f722e54874a8bd1eadd7 /arch/arm/boot/dts/socfpga.dtsi | |
| parent | ARM: dts: arria10: update NAND clocking (diff) | |
| download | linux-dev-0ffc5df823dd3495441c47ea3ffaa09d4a57a5f1.tar.xz linux-dev-0ffc5df823dd3495441c47ea3ffaa09d4a57a5f1.zip | |
ARM: dts: socfpga: update NAND clocking for c5/a5
The NAND IP needs 3 clocks(nand_x_clk, nand_clk, and nand_ecc_clk). The
nand_x_clk and nand_ecc_clk are derived from the nand_clk. The nand_x_clk
has a fixed divider of 4.
Also, update the NAND dts property with the correct clocks property.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: add nand_ecc_clk and update commit message
Diffstat (limited to 'arch/arm/boot/dts/socfpga.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/socfpga.dtsi | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index b38f8c240558..daf249e57b08 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -483,10 +483,17 @@ clk-gate = <0xa0 9>; }; + nand_ecc_clk: nand_ecc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&nand_x_clk>; + clk-gate = <0xa0 9>; + }; + nand_clk: nand_clk { #clock-cells = <0>; compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clocks = <&nand_x_clk>; clk-gate = <0xa0 10>; fixed-divider = <4>; }; @@ -754,7 +761,8 @@ reg-names = "nand_data", "denali_reg"; interrupts = <0x0 0x90 0x4>; dma-mask = <0xffffffff>; - clocks = <&nand_x_clk>; + clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; + clock-names = "nand", "nand_x", "ecc"; status = "disabled"; }; |