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| author |   Krzysztof Kozlowski <krzk@kernel.org> | 2020-06-26 10:06:02 +0200 |
|---|---|---|
| committer |   Dinh Nguyen <dinguyen@kernel.org> | 2020-07-15 14:13:00 -0500 |
| commit | d7adfe5ffed9faa05f8926223086b101e14f700d (patch) | |
| tree | b04b7a139b3457e58267f5b8b36d1ff92b57b2d7 /arch/arm/boot/dts/socfpga.dtsi | |
| parent | arm64: dts: stratix10: increase QSPI reg address in nand dts file (diff) | |
| download | linux-dev-d7adfe5ffed9faa05f8926223086b101e14f700d.tar.xz linux-dev-d7adfe5ffed9faa05f8926223086b101e14f700d.zip | |
ARM: dts: socfpga: Align L2 cache-controller nodename with dtschema
Fix dtschema validator warnings like:
l2-cache@fffff000: $nodename:0:
'l2-cache@fffff000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'
Fixes: 475dc86d08de ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC")
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/socfpga.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/socfpga.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index c2b54af417a2..78f3267d9cbf 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -726,7 +726,7 @@ }; }; - L2: l2-cache@fffef000 { + L2: cache-controller@fffef000 { compatible = "arm,pl310-cache"; reg = <0xfffef000 0x1000>; interrupts = <0 38 0x04>; |