diff options
| author |   Linus Walleij <linus.walleij@linaro.org> | 2018-10-08 13:27:55 +0200 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2019-04-17 23:18:47 +0200 |
| commit | f4bdfcc29a8bf96fc385a8221348781dd5594128 (patch) | |
| tree | ffad819d0389d0b7f2a0a9552ba168f6b5510c5e /arch/arm/boot/dts/ste-dbx5x0.dtsi | |
| parent | ARM: dts: ux500: Add Mali-400 (diff) | |
| download | linux-dev-f4bdfcc29a8bf96fc385a8221348781dd5594128.tar.xz linux-dev-f4bdfcc29a8bf96fc385a8221348781dd5594128.zip | |
ARM: dts: Ux500: Add MCDE and Samsung display
This adds and updates the device tree nodes for the MCDE
display controller and connects the Samsung display to
the TVK1281618 user interface board (UIB) so we get
nicely working graphics on this reference design.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/ste-dbx5x0.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/ste-dbx5x0.dtsi | 50 |
1 files changed, 39 insertions, 11 deletions
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 43d11346308e..81fabf031eff 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -1221,20 +1221,48 @@ }; mcde@a0350000 { - compatible = "stericsson,mcde"; - reg = <0xa0350000 0x1000>, /* MCDE */ - <0xa0351000 0x1000>, /* DSI link 1 */ - <0xa0352000 0x1000>, /* DSI link 2 */ - <0xa0353000 0x1000>; /* DSI link 3 */ + compatible = "ste,mcde"; + reg = <0xa0350000 0x1000>; interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + epod-supply = <&db8500_b2r2_mcde_reg>; + vana-supply = <&ab8500_ldo_ana_reg>; clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */ <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */ - <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */ - <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */ - <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */ - <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */ - <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */ - <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */ + <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */ + clock-names = "mcde", "lcd", "hdmi"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + dsi0: dsi@a0351000 { + compatible = "ste,mcde-dsi"; + reg = <0xa0351000 0x1000>; + vana-supply = <&ab8500_ldo_ana_reg>; + clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>; + clock-names = "hs", "lp"; + #address-cells = <1>; + #size-cells = <0>; + }; + dsi1: dsi@a0352000 { + compatible = "ste,mcde-dsi"; + reg = <0xa0352000 0x1000>; + vana-supply = <&ab8500_ldo_ana_reg>; + clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>; + clock-names = "hs", "lp"; + #address-cells = <1>; + #size-cells = <0>; + }; + dsi2: dsi@a0353000 { + compatible = "ste,mcde-dsi"; + reg = <0xa0353000 0x1000>; + vana-supply = <&ab8500_ldo_ana_reg>; + /* This DSI port only has the Low Power / Energy Save clock */ + clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>; + clock-names = "lp"; + #address-cells = <1>; + #size-cells = <0>; + }; }; cryp@a03cb000 { |