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authorChen-Yu Tsai <wens@csie.org>2017-06-09 23:34:36 +0800
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-06-10 11:24:39 +0200
commit7a78ef92cdc5813cab2c3a8ca2334eaaedc6818c (patch)
tree16ba0687f5580e317eb83ed7a2abe97c1c6a4ddd /arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
parentarm: sun8i: orangepi-zero: Enable dwmac-sun8i (diff)
downloadlinux-dev-7a78ef92cdc5813cab2c3a8ca2334eaaedc6818c.tar.xz
linux-dev-7a78ef92cdc5813cab2c3a8ca2334eaaedc6818c.zip
ARM: sun8i: h3: Enable EMAC with external PHY on Orange Pi Plus 2E
The Orange Pi Plus 2E, unlike the Orange Pi PC and PC Plus which its schematics are based on, uses an external Realtek RTL8211E PHY in RGMII mode, with a GPIO enabling the regulator for I/O signalling power supplies. The PHY's main power supply is enabled by the main 5V power supply. Add the regulator and PHY nodes, and override the PHY phandle under the EMAC node, so that the EMAC works properly on this board. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts')
-rw-r--r--arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts26
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
index 5851a47a3089..80026f3caafc 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
@@ -50,4 +50,30 @@
/ {
model = "Xunlong Orange Pi Plus 2E";
compatible = "xunlong,orangepi-plus2e", "allwinner,sun8i-h3";
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+ };
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
};