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| author |   Maxime Ripard <maxime.ripard@bootlin.com> | 2019-05-25 15:09:19 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2019-06-06 12:56:01 +0200 |
| commit | 65a4a40215a9488c5dd04c9f2e313cd36c9475fa (patch) | |
| tree | 610f38e9030914481c2aeaadb2c30cd3460539bf /arch/arm/boot/dts/sun8i-v3s.dtsi | |
| parent | ARM: dts: sun6i: Add external crystals accuracy (diff) | |
| download | linux-dev-65a4a40215a9488c5dd04c9f2e313cd36c9475fa.tar.xz linux-dev-65a4a40215a9488c5dd04c9f2e313cd36c9475fa.zip | |
ARM: dts: sun8i: v3s: Fix the RTC node
For some reason, while the v3s has a dedicated compatible in the RTC
binding, the one actually used was the A31's. However, it turns out that
the controller is pretty different (which justified the compatible).
Let's use the proper compatible, and use the proper binding description as
well.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'arch/arm/boot/dts/sun8i-v3s.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sun8i-v3s.dtsi | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index df72b1719c34..6ba9377458b3 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -91,7 +91,7 @@ #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; - clock-output-names = "osc32k"; + clock-output-names = "ext-osc32k"; }; }; @@ -264,17 +264,20 @@ ccu: clock@1c20000 { compatible = "allwinner,sun8i-v3s-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; + clocks = <&osc24M>, <&rtc 0>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; }; rtc: rtc@1c20400 { - compatible = "allwinner,sun6i-a31-rtc"; + #clock-cells = <1>; + compatible = "allwinner,sun8i-v3-rtc"; reg = <0x01c20400 0x54>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc32k>; + clock-output-names = "osc32k", "osc32k-out"; }; pio: pinctrl@1c20800 { @@ -282,7 +285,7 @@ reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; |