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| author |   Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-01-23 17:55:30 +0900 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2016-04-12 17:09:28 +0200 |
| commit | 955d809bdeaea3663cf6ac1ee72cd50775bbab9d (patch) | |
| tree | 8cc239724e40264746c379065f322ffa7a50d482 /arch/arm/boot/dts/tegra114.dtsi | |
| parent | Linux 4.6-rc1 (diff) | |
| download | linux-dev-955d809bdeaea3663cf6ac1ee72cd50775bbab9d.tar.xz linux-dev-955d809bdeaea3663cf6ac1ee72cd50775bbab9d.zip | |
ARM: tegra: Remove redundant ARM_L1_CACHE_SHIFT_6 select
These two are both ARMv7 SoCs. They need not explicitly select
ARM_L1_CACHE_SHIFT_6 because it is enabled along with CPU_V7.
Refer to commit a092f2b15399 ("ARM: 7291/1: cache: assume 64-byte L1
cachelines for ARMv7 CPUs").
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra114.dtsi')
0 files changed, 0 insertions, 0 deletions