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| author |   Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2018-09-01 15:04:57 +0200 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2018-09-26 16:50:38 +0200 |
| commit | e0cffa9a1b64099f537887712ba3802f92429675 (patch) | |
| tree | 11a0b1aef873a965d1d0f919a65ce5944bae4c8b /arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | |
| parent | ARM: tegra: apalis-tk1: add toradex, apalis-tk1-v1.2 compatible (diff) | |
| download | linux-dev-e0cffa9a1b64099f537887712ba3802f92429675.tar.xz linux-dev-e0cffa9a1b64099f537887712ba3802f92429675.zip | |
ARM: tegra: apalis-tk1: reorder cpu dfll clock properties
Reorder CPU DFLL clock properties.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 37e443e21ce6..07dd208296d3 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -1925,8 +1925,8 @@ /* CPU DFLL clock */ clock@70110000 { status = "okay"; - vdd-cpu-supply = <®_vdd_cpu>; nvidia,i2c-fs-rate = <400000>; + vdd-cpu-supply = <®_vdd_cpu>; }; ahub@70300000 { |