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| author |   Thierry Reding <treding@nvidia.com> | 2020-06-11 19:50:22 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-06-25 09:29:44 +0200 |
| commit | 5b66a2b43f19551c3c6b15594d21a24a13505403 (patch) | |
| tree | 086d1ea5787d72a389c1330c765dbb18940aeac0 /arch/arm/boot/dts/tegra124.dtsi | |
| parent | ARM: tegra: Add #reset-cells to Tegra124 memory controller (diff) | |
| download | linux-dev-5b66a2b43f19551c3c6b15594d21a24a13505403.tar.xz linux-dev-5b66a2b43f19551c3c6b15594d21a24a13505403.zip | |
ARM: tegra: Fix order of XUSB controller clocks
This is purely to make the json-schema validation tools happy because
they cannot deal with string arrays that may be in arbitrary order.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra124.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra124.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index ea4cf054fb3b..c03df6a3a9e0 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -680,8 +680,8 @@ <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, <&tegra_car TEGRA124_CLK_XUSB_SS>, - <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, <&tegra_car TEGRA124_CLK_PLL_U_480M>, @@ -689,7 +689,7 @@ <&tegra_car TEGRA124_CLK_PLL_E>; clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src", "xusb_ss", - "xusb_ss_div2", "xusb_ss_src", + "xusb_ss_src", "xusb_ss_div2", "xusb_hs_src", "xusb_fs_src", "pll_u_480m", "clk_m", "pll_e"; resets = <&tegra_car 89>, <&tegra_car 156>, |