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| author |   Nicolas Chauvet <kwizart@gmail.com> | 2015-08-08 15:58:12 +0200 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2015-08-21 18:44:28 +0200 |
| commit | 0d5ccb38d19574fecfa471205317d37221ec59a7 (patch) | |
| tree | b928c9fe5a9c6ab180220755d100aaf94a12eea5 /arch/arm/boot/dts/tegra20.dtsi | |
| parent | ARM: tegra: Add Tegra124 PMU support (diff) | |
| download | linux-dev-0d5ccb38d19574fecfa471205317d37221ec59a7.tar.xz linux-dev-0d5ccb38d19574fecfa471205317d37221ec59a7.zip | |
ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114
Current base address is wrong by 0x04 bytes for AHB bus device as shown
in dmesg:
tegra-ahb 6000c004.ahb: incorrect AHB base address in DT data - enabling workaround
To correct old DTBs, commit ce7a10b0ff3d ("ARM: 8334/1: amba: tegra-ahb:
detect and correct bogus base address") checks for the low bit of the
base address and removes theses 0x04 bytes at runtime.
This patch fixes the original DTS, so upstream version doesn't need the
workaround of the base address.
As both addresses are valid, this patch doesn't break compatibility.
Tested on tegra20-paz00 (aka ac100).
Signed-off-by: Nicolas Chauvet <kwizart@gmail.com>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra20.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index f444b67f55c6..f6f1461a7cde 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -225,9 +225,9 @@ #dma-cells = <1>; }; - ahb@6000c004 { + ahb@6000c000 { compatible = "nvidia,tegra20-ahb"; - reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ + reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */ }; gpio: gpio@6000d000 { |