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| author |   Stephen Warren <swarren@nvidia.com> | 2013-01-23 09:43:49 -0700 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-01-28 11:24:09 -0700 |
| commit | abf80c276dca1bf40b342b4ebf7815be0f6ba564 (patch) | |
| tree | 4b90282b64e4f0b74200c120c96206c052dd6dfa /arch/arm/boot/dts/tegra20.dtsi | |
| parent | ARM: tegra: Add Toradex Iris carrier board DT with T20 512MB COM (diff) | |
| download | linux-dev-abf80c276dca1bf40b342b4ebf7815be0f6ba564.tar.xz linux-dev-abf80c276dca1bf40b342b4ebf7815be0f6ba564.zip | |
ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi
No Tegra30 Platform is running PLL_P at another rate than 408MHz, nor is
any using any other PLL as UART source clock. Move attribute into SoC
level dtsi file to slim down board DT files.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20.dtsi')
0 files changed, 0 insertions, 0 deletions